资源列表
intcount
- 用整数形式实现四位加法计数器的一个源程序
addersubtractor10
- vhdl coding for adder subtractor used in dct
counter
- 计数器的VHDL源码及其对于的仿真Testbench 文件的编写-VHDL Code about counter for the "Simple Test Bench" example VHDL Code about adder for the "Simple Test Bench" example
MyCounter
- 可自由配置的通用计数器，我设计的时候一直在用
gaxgq16
- 16位并行相关器的VHDL程序-16 parallel with the VHDL-related procedures
barrel_shifter
- VHDL实现的桶型移位器，能在一个时钟周期实现对数据的（0－12位）算术右移-VHDL implementation of a barrel—shifter, able to achieve at one clock cycle of data (0-12 bit) Arithmetic Shift Right
pwm
- 用 硬件描述语言实现脉宽调制 VHDL 例子-PWM through VHDL
64B_adder
- Verilog HDL 64位并行加法器,并且还含有测试文件，可供测试-Verilog HDL 64-bit parallel adder, and also contains a test file, ready for testing
signed_mul
- signed multiplication verilog module
huxi
- 基于VHDL设计四个频率不同的呼吸灯，呼吸频率分别为 0.1Hz,0.2Hz，0.4Hz，0.8Hz 呼吸灯原理：利用PWM波控制led的亮度，的 原始代码 quartus软件亲测可用。-VHDL-based design in four different frequencies breathing light, breathing frequency was 0.1Hz, 0.2Hz, 0.4Hz, 0.8Hz breathing light principle: the use PWM
fifo
- first in first out buffer
TXcontrol
- 在一个具有编解码，调制解调等的简单通信系统的硬件仿真中，发送端的时隙控制的VHHL源码-In emulation of a codec, modem, etc. have a simple communication system, the sender of the control slot VHHL source