资源列表
s2p.rar
- 串并转换功能，采用VERILOG语言编写，包括测试文件，与大家分享，供大家参考,SERDES function, the use of language VERILOG, including the test documents to share with you, for your information
mult_addtree
- 用VERILOG HDL 语言实现一个4位的流水线乘法器-VERILOG HDL language with a 4-bit pipelined multiplier
fir_memory
- 用memory编写的verilog代码，可用于工程应用，已经过仿真-Verilog code written with the memory can be used for engineering applications, has been simulation
clk_111k
- Clock baud rate modifier
vhdlcodes2
- VHDL coding for a 4 bit comparator in structural and behavioural modelling.
licznik8bit
- 8 bit counter created in vhdl as a program to complete one of my study case.
1
- 本程序成功描述了如何用单片机对温湿度传感器进行控制-This procedure describes how to successfully use the microcontroller to control the temperature and humidity sensor
Counter
- best simple counter for verilog modelsim6.5
add_tree_mult
- verilog HDL编写的8位乘法器，谢谢使用-the preparation of 8-bit multiplier verilog
cx
- 变模可逆计数器的VHDL功能描述，是数字锁相环的一个期间的程序-Reversible counter variable mode
stream_to_asc
- 将二进制码流转换为ASICII文件,可做fpga码表-from bianry streams to ASICII
LPLFSR
- LPLFSR for low power pattern generation.