资源列表
fuyong
- 四路四bit时分复用复接器设计,完成拨码开关式输入的复接器。-Four-four time division multiplexing bit multiplexer designed to complete the DIP switch inputs of the multiplexer.
ALU_finished
- 8bit四级流水ALU 其中有乘法器除法器加法器减法器开方 移位逻辑运算等等通过顶层来控制选择输出需要的运算值-8bit four water which has a multiplier divider ALU adder subtracter prescribing controlled shift logic operations so operators need to select the output value by the top
mdio_mdc
- mdio verilog 实现-mdio verilog coding
Vendor
- 用verilog编写的自动售货机,基于Basys2平台,共有3种物品可以选,分别为4元,2.5元,1元,可以投入3种类型的货币,分别为1元,5元,10元,共有5个状态。-This is a vending machine which is written by verilog on Basys2 board.
FPGA_CRC
- 用Quartus II 13.0 (32-bit)实现并行计算8位数据宽度的CRC16-CCITT循环冗余码,verilog HDL源代码,并有本人手工计算的原理。本程序已经过ModelSim-Altera模拟,仿真波形文件都在本文件内。-Calculated using the Quartus II 13.0 (32-bit) parallel 8-bit data width CRC16-CCITT cyclic redundancy code, verilog HDL source cod
A_PUF_Design
- 基于fpga的物理不可克隆函数(PUF)模块的实现-A PUF Design for Secure FPGA-Based Embedded Systems
graduate
- 基于fpga的IIR和FIR滤波器实现,里面有DA和AD模块,已经下载到板子上验证。-IIR and FIR filter fpga-based implementation, which has DA and AD modules have been downloaded to authenticate to the board.
dsp320vc33_20020210.tar
- dsp 320 in vhdl.code for sram also included.
phyjingjian
- 通过fpga对phy芯片88e1111进行控制,可改变工作模式,传输速度等。-By fpga control of phy chip 88e1111 can change the working mode, the transmission speed.
pingpangqiu
- 基于basys2的简单的乒乓球小游戏,通过ise13.4开发,使用语言VHDL,能够通过VGA在显示屏显示,能够实现双人对打,有计分功能。-Simple table tennis game, based on basys2 through ise13.4 development, using VHDL language, can through the VGA display shows, can achieve a double play, scoring function.
ds769_axi_slave_burst
- xilinx AXI4 slave burst 接口的介绍文档,有助于理解IP核-The introduction of xilinx AXI4 slave into the interface documentation
RGB-to-YCbCr[Verilog]
- 基于FPGA平台的颜色色彩空间转换 RGB to YCbCr-Based on the FPGA platform color RGB to YCbCr color space transformation