资源列表
8adder
- 本实验示例中的8 位二进制并行加法器即是由两个4 位二进制并行加法器级联而成 的图13-4 所示的逻辑电路是由两个并行进位4 位加法器级联而成的8 位二进制加法 器-This is simple adder of 8 by VHDL.
tolltax
- toll tax coding in microcontroller
vgacode
- VGA彩条信号发生器，从网上搜到的，希望对大家有用-VGA color bar generator, search the web, and we hope to be useful
tlc5620
- 模数转换的verilog描述，比较适合于初学者的学习-DA of Verilog
dpll2
- 数字锁相环的vdhl实现，鉴相器，计数器，压控振荡器，和分频器-Vdhl DPLL implementation, the phase detector, a counter, a voltage controlled oscillator, and a frequency divider
ovsf
- 正交扩展稀疏码 在FPGA中实现 代码内容可靠 可以在硬件平台实现。-Sparse orthogonal spreading codes to achieve a reliable source content in FPGA can be implemented in hardware platform.
hdb3decode
- g.703 hdb3 decode verilog source code
50M-1
- VHDL语言。。如何实现50MHz分频为1Hz，的用意应该是考核你的4M如何分出来，注意看我的注释-VHDL language. . How to achieve 50MHz sub-band is 1Hz, the intention is assessing your 4M how to sub-out, pay attention to my comment
led_display
- 用fpga芯片实现7段数码管静态显示7128-Using the fpga chip realize 7 period of digital tube static display 7128
memory
- The pipeline SPIN VHDL code (memory part)
random
- 8位伪随机序列发生器。在通信加扰，序列检测中有很强的工程应用-8 pseudo-random sequence generator. In communications scrambling sequence detection has a strong engineering applications
servo_pwm
- is basic servo pwm DE2-116