资源列表
macunit
- it is he design of mac unit
VHDL
- 用VHDL写的代码，实现任意整数分频，自己只要修改分频参数即可。希望对大家有用-Written in VHDL code used to achieve arbitrary integer frequency, their frequency as long as the modified parameter. We hope to be useful
Serialadder
- VHDL语言串行加法器 可以实现五位加法运算-Serial adder five addition operations can be achieved
penc81
- 8:1 priority encoder.. Test Bench included-8:1 priority encoder.. Test Bench included..
div_nonrestoring
- 用verilog 实现的除法器 ，被除数32位 除数为16位-Divider using verilog realize the dividend 32 divisor is 16
pwm_auto
- PWM for VHDL program
ram_sp_sr_sw
- 同步读/写 RAM，使用systemverilog实现-Synchronous read write RAM, using systemverilog
ram_sp_sr_sw.v
- this is a verilog source code for Single Port RAM Synchronous Read/Write.
6fenpin
- 毕业设计里面的一个模块，主要实现时钟6分频的功能-The inside of the graduation design a module, mainly realizes the clock frequency function of six points
new
- qpsk的vhdl实现代码 qpsktiaozhi的vhdl实现代码 -String and conversion
bch_codeword11
- 3072 to 3240 vhdl encoder source code
m
- 为随机序列产生器，可以作为调制信号的信源-As the random sequence generator, can be used as a modulation signal source