资源列表
my_gold
- 基于FPGA的gold码发生器，用VHDL语言编写的源程序。-The gold code generator based on FPGA, VHDL language with the source.
drive
- TCD1300ccd的驱动，是用 Verilog实现的
1
- 频率计程序cpld-Frequency counter counting procedures
ade
- 用verilog HDL语言实现一个8位串行乘法器-An 8-bit serial multiplier with Verilog HDL language
filtru_fi
- This is a filter fir implemeted in vhdl, i hope it will work :)
seg9999
- 数码管动态显示的VHDL程序，显示小时，分钟，秒，动态显示的初级程序，可供初学者的参考-for
single_port_rom
- rom implemention in verilog hdl
mux
- mux选通，每两个输入，通过选择输出其中一个信号-gated mux, each of the two inputs, one output signal by selecting
runtest
- chirp trip for beginners
fsm
- truong trinh mau cho viet fsm cu vhdl
Dlatch3
- 基于VHDL的触发器设计。 由一个电平触发的D触发器构成的上下边沿触发器。-Trigger-based VHDL design. Consists of a level-triggered D flip-flops up and down the edge of the trigger.
mapperSharp1(16QAM)
- This the code for the mapper in the verilog code.-This is the code for the mapper in the verilog code.