资源列表
booth
- 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
Abus_fifo_ram_V1
- 该模块是基于verilog语言编写的双口ram模块，可将该该模块作为缓存模块使用-surpost ram write/read
lcd-16x2-arduino-lcd-codes
- Source code print caracter to lcd 16x2 from arduino modules
strobe_gen
- 分频功能，clk,reset为输入端口，分频系数10，时钟为25mhz。-Divide function, to obtain the required clock.
crc-ccitt
- CRC校验ccitt的串行功能实现，实现16位CRC校验，校验方式是CCI-function of realize crc ccitt 16BIT
crc
- CRC循环冗余校验 CRC循环冗余校验 -Cyclic redundancy check
yinyue_yanzou_module
- 蜂鸣器实现音乐单调，通过控制频率从而控制单调的产生。-Buzzer to achieve music monotonous, monotonous by controlling the frequency to control the production.
TD1_11
- add soubstraction td 1 VHD L SCHOOL HOME WORK EASY NOT DIFFICULT ZIP RAR GZ-add soubstraction td 1 VHD VHDL SCHOOL HOME WORK EASY NOT DIFFICULT ZIP RAR GZ
gmsk_new
- GMSK vhdl experimented as alternative function it is implemented in VHDL.
daojishi
- 基于VHDL编写的60S倒计时，可以设置倒计时开始时间， 重置倒计时，倒计时结束数码管会闪烁，蜂鸣器报警，quartus软件亲测可用。-60S-based VHDL, countdown, countdown start time can be set, reset the countdown, countdown to the end of the LED will blink, buzzer alarm, quartus software pro-test available.
txd_control
- uart串口发送控制模块 适合于485 422 232等接口-uart TXD——contrl Verilog
fm0_encode
- fm 0 encode source code by using verilog