资源列表
booth
- 基于verilog的booth算法的乘法器-Based on the booth algorithm verilog multiplier
VGA_Ctrl
- 基于NIOS II 的DE1开发板的VGA 控制器VGA控制模块主要控制VGA模块的开始和其运行的状态，需要写一个Avalon 从端口响应CPU的控制信号，继而控制整个模块的运行，-Based on the DE1 of the NIOS II development board VGA controller to control the VGA module VGA main control module and its operation began, and the need to wri
traffic
- 交通灯的VHDL实现，使用状态机来实现，适合初学者-VHDL implementation of traffic lights, use state machines to implement, suitable for beginners
LEDs
- LEDs VHDL源码 经修改,功能正常,可综合.-LEDs VHDL source code
rcrc16
- rcrc16的反校验码，用于接收方的校验，工程上已经实现了，是正确的代码-rcrc16 anti-check codes for the receiver calibration, engineering has been achieved, is the correct code
crc
- CRC循环冗余校验 CRC循环冗余校验 -Cyclic redundancy check
yinyue_yanzou_module
- 蜂鸣器实现音乐单调，通过控制频率从而控制单调的产生。-Buzzer to achieve music monotonous, monotonous by controlling the frequency to control the production.
TD1_11
- add soubstraction td 1 VHD L SCHOOL HOME WORK EASY NOT DIFFICULT ZIP RAR GZ-add soubstraction td 1 VHD VHDL SCHOOL HOME WORK EASY NOT DIFFICULT ZIP RAR GZ
gmsk_new
- GMSK vhdl experimented as alternative function it is implemented in VHDL.
daojishi
- 基于VHDL编写的60S倒计时，可以设置倒计时开始时间， 重置倒计时，倒计时结束数码管会闪烁，蜂鸣器报警，quartus软件亲测可用。-60S-based VHDL, countdown, countdown start time can be set, reset the countdown, countdown to the end of the LED will blink, buzzer alarm, quartus software pro-test available.
txd_control
- uart串口发送控制模块 适合于485 422 232等接口-uart TXD——contrl Verilog
fm0_encode
- fm 0 encode source code by using verilog