资源列表
count
- 自己编制的计数器的verilog代码 希望能对大家有所帮助
sseg
- vhdl codefor 7 segment display
24add
- 24进制it describe how to design a add24-it describe how to design a add24
USB
- 这个是Verilog的USB控制程序，用于USB与FPGA之间的通信-This is the USB Verilog control procedures for the communication between USB and FPGA
m_vhdl
- 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器，采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值（程序中设定好四种非零初值可选）-m sequence vhdl
CRC10
- CRC校验 自己编写的程序，通过matlab仿真-CRC check
fifo
- 用VHDL语言写的FIFO代码，可设FIFO的深度-VHDL language with code written in FIFO, FIFO depth can be set up
mux41we
- 4:1 multiplexer using with select.. Test Bench included-4:1 multiplexer using with select.. Test Bench included..
duble-process-lock
- 编写由两个主控进程构成的与上述功能相同的符号化Moore型有限状态机-The process of writing composed by two main control functions with the same symbol of Moore-type finite state machine
lcd1602
- verilog写的v5板子1602测试程序 可以直接使用 已测试-this is a code applied for lcd1602 in v5
read_file_test
- VHDL读写文件范例，仿真专用，验证通过-Examples of VHDL to read and write files, simulation-specific, verified by
addsub
- This code implement add or sub between 2 number