资源列表
MediaMobile
- moving average vhdl source code
asyncwrite
- FPGA异步时序转同步时序模块 位宽（bit） -FPGA asynchronous transfer timing synchronization timing module Width (bit)
conv
- conv clock code for any thing
NO2_SWITCH_IF
- swiych_if by vhdl using xlinx
8-bitinput-output-shift
- 8位串行输入，串行输出移位寄存器 VHDL-8-bit serial input, serial output shift register VHDL
max5822
- Arduino Program for pulsing the brightness of an LED connected to a MAX5822 DAC chip to Arduino Duemilanove Microcontroller. 88 is the I2C address of the DAC chip, Please refer to MAXIM s official datasheet for better understanding of the DAC
main
- 实现两个8°的音阶，储存有一首音乐，用lcd显示-Two 8 ° scale, stored in a music, with lcd display
basketball24
- 基于FPGA的篮球24秒计时器，开发环境为MAXPLUS-24 second timer in the FPGA-based basketball,Development environment for MAXPLUS
1M
- 一分频的VHDL程序，内容介绍非常详细，希望能给大家带来方便，很实用的-Divide the VHDL program, introduced in great detail, and the hope that they can bring convenience to very practical
seqdet_vm
- 在verilog下连续输入1和0，当输入为10010时输出为1，是初学者练习用的-In verilog continuous input 1 and 0, when the input is 10010 to 1 when the output is used for beginners to practice
gen_clk
- 占空比可变的信号发生器 解释的好麻烦那 不知道怎么解释-A variable duty cycle signal generator
baud_control
- uart串口波特率控制，和uart——top uart——rxd_contrl 等随模块联合使用-uart baud clk Verilog