资源列表
edge_check2
- 一种实用的上升沿检测程序，可用于上升沿检测，或根据上升沿生成高低电平等-Rising edge of a practical testing procedure can be used for rising edge detection, or generated in accordance with the high-low, such as rising edge
ModifyInstruction
- 数字环路滤波器是由变模可逆计数器构成的。 该计数器设计为一个17 位可编程(可变模数) 可逆 计数器,计数范围是,由外部置数DCBA 控制-Digital loop filter is composed of variable-mode reversible counter. The counter is designed to a 17-bit programmable (variable modulus) reversible counter, counting range is s
fpga-4
- VGA controller and display wit h eight coloreight coloreight coloreight color s displayedisplaye displayedisplayedisplayed in a fixed ordea fixed orde a fixed orde a fixed ordea fixed orde a fixed order.
uart_tx
- uart transmitter module in verilog hdl
encrypt_8
- This vhdl source is top level entity. TEA algorithm to encrypt 8-bit data.
pwm16bit
- 可以产生16位pwm波，脉宽可调，频率固定，可以作为学习资料。-Can generate 16-bit pwm wave, pulse width adjustable, fixed frequency, can be used as learning materials.
comparator-using-vhdl
- vhdl code for comparator
N-jishu-fenpin
- N倍奇数分频器源码,可根据需要修改N数字即可-N times odd divider source
gdi1
- Viterbi decoder is used for decoding data encoded using Convolution Forward Error Correction codes or data that suffers inter-symbol interference. They occur in a large proportion of digital transmission. Viterbi decoders employed in digital wire
sram_16bit_512k
- FPGA 的sram controller -it is a certifed sram controller
ads7822
- verilog 编写的ads7822的控制与数据保存，已仿真通过-verilog written ads7822 control and data saved through simulation
Adder_Array
- 用verilog 实现了一个加法器阵列的计算，32位，位数可以扩展。-Verilog achieved by calculating an adder array 32, the median can be extended.