资源列表
1M
- 一分频的VHDL程序，内容介绍非常详细，希望能给大家带来方便，很实用的-Divide the VHDL program, introduced in great detail, and the hope that they can bring convenience to very practical
seqdet_vm
- 在verilog下连续输入1和0，当输入为10010时输出为1，是初学者练习用的-In verilog continuous input 1 and 0, when the input is 10010 to 1 when the output is used for beginners to practice
gen_clk
- 占空比可变的信号发生器 解释的好麻烦那 不知道怎么解释-A variable duty cycle signal generator
counter
- Counter for VHDL. I have made a 3 bit COunter for my stopwatch project. -Counter for VHDL. I have made a 3 bit COunter for my stopwatch project.
MAX134_ctrl
- verilog 万用表芯片MAX134的写控制字，代码，控制-verilog MAX134 control
motor
- 用Verilog HDL语言实现四相步进电机前进，后退-Verilog HDL language with four-phase stepper motor forward and backward
TLC5510
- TLC5150 VHDL控制程序，代码很详细，已经调试通过-TLC5150 VHDL control program, the code is very detailed, have been debug through
Vhdl1
- 简单的实用VHDL语言编写的LED跑马灯程序-Simple and practical LED Marquee VHDL language program
code
- 设计一个同步二十四进制计数器，理解触发器同步计数工作机制，掌握同步触 发控制的VHDL描述方法以及异步清零的描述方法。 -Design a synchronous binary counter twenty-four understanding count the trigger synchronization mechanism, master synchronous trigger VHDL descr iption method and asynchronous clear desc
data_sel
- 数据选择器的作用是根据不同的输入信号，产生相应的输出信号。例如地址译码器就 是一种数据选择器。这里设计的是一个2-4 数据选择器，根据2 位宽输入信号的变化，4 位宽的输出信号会产生不同的结果。数据选择器属于组合逻辑电路。-Data selector according to the role of the different input signals, generates a corresponding output signal. For example, an address d
kn_cnt16.v
- 可逆的异步计数器-Reversible asynchronous counter! ! ! ! ! ! ! ! ! ! ! ! !
baud_control
- uart串口波特率控制，和uart——top uart——rxd_contrl 等随模块联合使用-uart baud clk Verilog