资源列表
CRC32
- 基于FPGA平台的用verilogHDL设计的CRC32模块-a code for CRC32 based on FPGA by verilogHDL
clk_gen
- 基于vhdl的分频器模块设计，已经经过调试，可直接调用-Divider vhdl module based on the design, debugging has been directly call
less
- Less for VHDL Project
clkdiv
- 初学者一个比较容易入门的FPGA verilog 二分频实验。-Relatively easy for beginners to get into a FPGA verilog two-way experiment.
simple_test
- This a vhdl code for colour converter fpga code for testing shape_gen code-This is a vhdl code for colour converter fpga code for testing shape_gen code
cfq8
- 基于Quartus仿真软件verilog语言的八位二进制乘法器，用于八位二进制乘法运算。-Based on Quartus simulation software of eight binary multiplier, verilog language used in eight binary multiplication.
jkff_behav.v
- This is JK-FF in Behavioural Style.
handshake
- Handshake module detection
CRC
- CRC 编码-CRC code. . . . . . . . . . . . . . . . .
dial
- 读入拨码开关8位0 1状态在8位7段数码管相应位上显示0或1。-Reads DIP switch 8 0 1 state in the 8-bit 7-segment display the corresponding bit 0 or 1.
2stageMillerC2012v6
- 带米勒补偿效应的二级运算放大器实现电路图，在Hspice中实现的代码-Two operational amplifiers with Miller compensation effect achieved schematics, code implemented in Hspice
arb
- verilog round robin arbiter