资源列表
crc16
- crc16 module for SDIO DAT line calculation
IIR_Filter
- 一个简要的低通滤波程序IIR Filter QuartusII7-IIR Filter QuartusII7
counter
- vhdl code for counter
clk_generator
- 时钟分频代码，PWM产生 RTL 源代码。-clock divider，PWM generator RTL Source Code
d_ff_cout_tb
- D FLIP FLOP TEST BENCH
seg
- 数码管显示（verilog） 自己写的 在数码管上显示01234567 动态显示-Digital LED display (verilog) himself wrote in the digital tube display 01234567 dynamic display
adder16_2
- 16位2级流水线加法器的Verilog设计-16 2 pipeline adder Verilog Design
transpose_buffer
- verilog source code for transpose buffer 8x8 matrics
testmult_top
- TESTBENCH测试程序，小数加法器的实现，小数位设为2位，将其小数位与整数位分别显示出来。-TESTBENCH test procedures, the implementation of decimal adder, is set to two decimal places, its decimal places, respectively, with the integer-bit display.
FIR
- 10阶的F.I.R滤波器设计的 verilog代码-Verilog code for the 10-order FIR filter design
div
- 两个3位二进制数的除法，结果（整数商）输出到数码管显示-verilog multply
ram
- vhdl code for simple ram block