资源列表
led7drv
- 7段LED驱动器的VHDL语言程序设计源码-7 segment LED driver source VHDL Language Program Design
lock
- 设计一个8位串行数字密码锁控制电路 -Design an 8-bit serial digital code lock control circuit
shigfr
- 循环移位，实现cpld控制dac的数据采集，分时传输来那个词数据-Cyclic shift, to achieve control dac cpld data collection, sharing of data transmission to the word
carry-save-multiplier-Verilog-code
- 进位存储乘法器Verilog代码,该乘法器的显著特点是其性能取决于使用的硬件而与数据长度无关.-carry save multiplier Verilog code
add4
- 加法器的verilog代码，描述一个四位的加法器，可移植性很强，适合很多场合。-The adder verilog code, describe a four of the adder, portability is very strong, suitable for many occasions.
qiduanxianshi
- Verilog代码段,包括七段数码管显示电路，调试通过的代码哦，很实用-Verilog code segments, including the seven-segment LED display circuit, code debugging through, oh, very practical
light-a-LED-lamp.
- 在FPGA开发板上点亮一个LED灯,型号为DB4CE15。-FPGA development board to light a LED lamp.
pwm
- 在Quartus 9.0 下实现的PWM IP核设计，周期占空比均可调。-PWM IP core design,which period and duty is adjustable.
sobel_verilog
- Based on this one-dimensional analysis, the theory can be carried over to two-dimensions as long as there is an accurate approximation to calculate the derivative of a two-dimensional image. The Sobel operator performs a 2-D spatial gradient measurem
exp9
- 本实验要完成的任务是设计一个四位二进制全加器。具体的实验过程就是利用实验系统上的拨动开关模块的SW17~SW14作为一个加数X输入，SW13~SW10作为另一个加数Y输入，用LED模块的LEDG0~LEDG4来作为结果S输出，LED亮表示输出‘1’，LED灭表示输出‘0’。-To complete the task of the experiment is to design a four bit binary full adder. The specific experimental proc
vhdldelay
- 用VHDL编写的一个软件延迟，比较好用，可以自己设定延迟时间。-Use VHDL to write a software delay, use, can set the delay time.
INS_Reg_Dec---Copy
- Instruction REgister