资源列表
DEF
- 一个简单的始终触发器的代码 另外包括测试验证程序和输入码数据
count
- 用VHDL实现一个四位十进制计数器来进行计数，并且仿真通过-To use VHDL to achieve a 4 decimal counter to count, and the simulation through the
ring
- Ring register[1 from 8] which seven speeds. The result is presented on 8 LEDs. After every cycle, speed grows. The process starts again after last 8 cycle.
clk_div
- 一个时钟分频模块,in verilog hdl-clock division module in verilog hdl
lcd
- FPGA嵌入式开发中的NIOSii的LCD1602控制程序。-FPGA NIOSii LCD1602
APU1
- 该程序主要实现迭代加法，实现128次迭代加法-The procedure to achieve iterative addition, to achieve the addition of 128 iterations
MA_HOA_MANCHESTER
- MANCHESTER ENCODING IN VHDL
7121
- SAA7121初始化文件,用于视频图像输出.-SAA7121 initialization files for video output.
Program5
- 设计一个 8 位数控分频器，将 8 位数控分频器扩展为 16 位数控分频器。 -Design an 8-bit digital divider, the 8-bit prescaler extended to 16-bit CNC CNC divider.
advhdl
- 此源程序是基于vhdl的AD转换模块，可用于FPGA的开发与应用-This source code is based on the VHDL AD conversion module, which can be used for development and application of FPGA
pisarenko
- 在频率差为10Hz以上，精度较高，输出正弦波频率，振幅和噪声功率-Frequency deviation of 10Hz, high accuracy, the output sine wave frequency, amplitude and noise power
EPM3032
- EPM3032上使用quartus5.0编写的verilog程序，用于单片机译码并驱动外设之用。-A verilog program used for embeded cpu encode and drive pheripha chip,platform is quartus5.0