资源列表
histogram4
- 利用matlab和modelsim完成了用直方图均衡化处理灰色图片的前仿真，有处理前后图片的对比，verilog语言编写，但到用实时处理还差很远-Completed using matlab and modelsim deal with the gray image histogram equalization before the simulation, a comparison of before and after pictures, verilog language, but with
FPGA--SDRAM
- SDRAM:Synchronous Dynamic Random Access Memory- 同步动态随机存储器，同步是指 Memory工作需要同步时钟，内部的命令的发送与数据的传输都以它为基准；动态是指存储阵列需要不断的刷新来保证数据不丢失；随机是指数据不是线性依次存储，而是自由指定地址进行数据读写。
FPGA读写SDRAM的实例
- FPGA对SDRAM进行读写测试程序，亲测有效无误。(FPGA reads and writes test programs for SDRAM.)
S02_CH02_MIO
- 基于ｖｉｖａｄｏ的ＭＩＯ点灯的实现，可以直接运行-Based on vivado MIO lighting implementation, you can run directly
S02_CH02_MIO
- xilinx zynq的mio口测试工程，内容很详细(zynq mio test,about zynq mio pin test,very useful)
LCD_controller
- 基础FPGA的LCD1602IP核设计,包括了硬体和软体的驱动，并有详细讲解-Using FPGA to designed the IP for lcd1602
Fre_Test
- VHDL语言频率计，需外围自行搭建整形电路。频率测量在1HZ-10MHZ精度为0.1 左右-VHDL frequency meter, a peripheral self build shaping circuit. The frequency measurement accuracy in 1HZ-10MHZ is about 0.1
upload
- 包含三个Project 两个开发板为altera FPGA，另一个为51板。功能：TFT 开发。 包含点亮测试，及OTP等。-Project 2 consists of three development boards for altera FPGA, the other for 51 boards. Function: TFT development. Contains the light test, and the OTP and so on.
黑金 AX545516开发板 Verilog 教程
- xilinx SPARTAN 开发板资料、及详细例程讲解(xilinx demo board designed example)
VHDL
- 滤波器的c语言实现，有较好的验证，能够运行的滤波器C语言-Filter c language, better validation, able to run the filter C language
基于FPGA实时视频图像网络传输系统设计
- 使用FPGA实现以太网的传输，通信方式为UDP(Using FPGA to achieve Ethernet transmission, communication mode is UDP)
LEON3_GRLIB_Source_grlib-gpl-1.3.7-b4144.tar-(1).
- Leon3 Ultra Sparc Compatible Processor