资源列表
adc0809
- VHDL实现AD采样控制，程序简单，调试方便-AD sampling control VHDL implementation, the program is simple and convenient debugging
CSDmultiplier
- Code for CSD Multiplier
ic7
- 具有奇校验功能的串行数据发送电路，用状态机实现。-Functions with odd parity of serial data transmission circuit, with the state machine implementation.
carLights-prelab
- vhdl sample of car lights which is a good example code for beginners for vhdl
adc08831
- 串行AD转换. 8位串行ADC输入,4次平均数输出.-8BIT SPI ADC
Automatic-beverage-vending-machine
- 自动售饮料机，只可投入5毛和1块钱，每瓶饮料为2.5元，要求应用状态机设计该系统，并编写Testbench。 输入信号定义： clk：时钟输入 ngreset：复位信号 half_yuan：五毛钱 one_yuan：一元钱 输出信号定义： dispense：表示机器售出一瓶饮料 collect：用于提示投币者取走饮料 half_out：表示找回五毛钱-Drinks vending machine can only be put into hair
eight
- 八位同步寄存器（检测时钟上升沿，一个接受复位信号，八位输入赋给八位输出）-eight bit registered
5b6b-decode
- 5b6b decode,verilog代码，已验证。-5b6b decode, verilog code has been verified.
clk-divide5
- 实现5分频计数的veriog电路，简单易懂，欢迎大家下载学习-Achieve 5 divider count veriog circuit, easy to understand, welcome to download the study
IIR_filter_design
- IIR滤波器的vhdl语言设计的简单滤波器-vhdl for iir filter
5
- 基于FPGA的数字秒表的VHDL设计,论文,有主要程序-FPGA-based VHDL design digital stopwatch, paper, a major program
8weishujusuocunqi
- 位数据锁存器，用于存储数据来进行交换，使数据稳定下来保持一段时间不变化，直到新的数据将其替换。 -8-bit data latch for storing data to be exchanged and the data stabilized for a period of time does not change until the new data to replace it.