资源列表
GPU_LDPC+硕士毕设论文详解
- QC LDPC的编码译码 代码与论文配套 是研究生毕设 可运行 代码风格优秀(QC LDPC Coding and Decoding Code and Paper Matching are Excellent Style of Running Code for Graduate Students)
axis_fifo
- VIVADO下使用verilog编码的axi fifo的简单使用，仿真通过，供初学者学习。-Use the following VIVADO verilog coding axi fifo simple to use, through simulation, for beginners to learn.
project_zynq
- 使用ZYNQ创建一个控制外设的MicroBlaze-Use ZYNQ to create a control peripheral MicroBlaze
noise
- 使用FPGA搭建NOISE||内核，在内核基础上进行工程建立。(Using the FPGA to build NOISE || kernel, based on the kernel to build the project.)
siga
- 2014电子设计大赛e题固件模块代码，很好的实现功能。-2014 electronic design contest e Title firmware module code, very good to achieve function.
clock
- 多功能数字钟，、在Quartus 2环境中编译通过； 4、仿真通过并得到正确的波形； 5、给出相应的设计报告 -clock
vhdl
- 《可编程逻辑器件和VHDL》的课件以及课后习题。可用于自学可编程逻辑器件和VHDL，很基础，适合初学者。-Programmable logic devices and VHDL courseware as well as after-school exercise. Can be used for self-programmable logic devices and VHDL, very basic, suitable for beginners.
Day-1-Training-Material
- OneSpin培训资料 OneSpin用于做断言验证。-OneSpin training material is used to study assertion verification in ASIC design.
通信协议FPGA
- 本设计是基于FPGA的高速并行接口通信接口和协议设计，该设计使用的是8 位并行接口，通过配置FPGA的FIFO寄存器保证了在高速并行下的数据稳定性，在 最终的测试中，该协议能够稳定传输的速度为80Mbps。(This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface
conv_encode
- 本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by c
THDB_ADA_v.1.4.2_SystemCD
- THDB_ADA光盘资料，包含全部资料，全部例程。-THDB_ADA CD-ROM contains all the information, all the routines.
Black-gold-Sparten6_VerilogV1.6
- 黑金Sparten6开发板Verilog教程V1.6，黑金FPGA教程，多种实例讲解，非常经典实用。-Black Gold Spartan6 board Verilog tutorials V1.6, black gold FPGA course, a variety of examples to explain, very classic and practical.