资源列表
SPI_TEST
- verilog SPI 读写时序，测试验证OK.-SPI Verilog Code, Master and Slaver.
clock_sel
- 无毛刺多时钟选择，可根据不同模式选择不同时钟(Multi clock selection, different modes can be selected according to different clock)
RCQ208_V3_24TFT
- Quartus NIOS例程，控制320*240TFT液晶显示，包括汉字、字符显示及显示缓存SDRAM控制驱动-Quartus NIOS routines, control 320* 240TFT LCD, including Chinese characters, character display and display control drive cache SDRAM
onchip_seg
- NIOS FPGA片上存储器的核12345673564-NIOS FPGA on-chip memory nuclear 12345673564
电梯控制器报告(Verilog实现)
- 实现一个简单的电梯控制器,能够完成一个四层电梯的控制(The realization of a simple elevator controller, to complete a four storey elevator control)
Q11_SOPC_Freq_Avalon
- FPGA平台下基于Nios II的数字频率计，测频模块采用verilogHDL编写，等精度算法，Avalon总线封装，Nios II读取最终的频率数值，显示在LCD12864上。-The Nios digital frequency meter based on II FPGA platform, the frequency measurement module written by verilogHDL, such as the accuracy of algorithm, Avalon bu
DEMO_N
- FPGA NOISII程序，包含串口，FLASH,SPI等各种接口的程序，由原理图和VERLOG语言混合编写，非常适合初学者，开发环境为QUARTUS 9.0，芯片为EP2C208QC8N-The the FPGA NOISII program, including serial, FLASH, SPI, interface program, the schematic and VERLOG language prepared by mixing, ideal for beginners, de
AN177
- AMBA Application Note: AN177 - Using EB with CT1176JZF-S Core Tile. -AMBA Application Note: AN177- Using EB with CT1176JZF-S Core Tile. This example shows how to use the EB baseboard with a CT1176JZF-S Core Tile. The following board combi
matlab
- 16位浮点FFT算法的VHDL实现有测试文件！-16-bit floating-point FFT algorithm VHDL realization of a test file!
dfilter
- 用FPGA实现信道化接收机算法，共256个信道，处理时钟40M，时分复用完成算法实现-FPGA implementation using channelized receiver algorithm, a total of 256 channels, processing clock 40M, time division multiplexing algorithm to complete
Viscosity_1.7.7[sn]
- Viscosicty is a vpn app
fft512_ipcore
- 512点的FFT 使用IP核 帮助新手理解-Using a 512-point FFT IP core to help the novice to understand