资源列表
systemverilog+assertions应用指南
- system verilog assertion介绍(system verilog assertion introduction)
Quartus_18.0_破解器_Windows密码12345
- Quartus_18.0_破解器_Windows密码12345(Quartus_18.0_crack_Windows,password:12345)
teacher_uart
- 由verilog编写的uart收发模块，能够在串口助手发送字符，并在数码管上显示，开发板为basys3 内置约束文件(The UART transceiver module written by Verilog can send characters to serial assistant and display them on the digital tube. the development board is built-in constraint file of basys3)
Xilinx_FPGA-macro-use
- xilinx fpga底层宏单元使用，讲的很详细，适合基础的入门学习(The use of Xilinx FPGA bottom macrocell is very detailed and suitable for basic entry learning.)
基于FPGA的负延迟设计
- 用VHDL语言写的基于FPFA的负延迟设计(FPFA based negative delay design written in VHDL language)
DDR_sdram
- 文件里有DDR3/DDR4 sram的verliog模型，而且具有DDR4参考书(The document has a verliog model of DDR3/DDR4 SRAM, and it has DDR4 reference books.)
Quartus_17.1破解器_Windows_密码12345
- quartus 17.1 安装包，我现在用的就是(Quartus 17.1 installation kit, what I am using now is)
emmc
- emmc协议的实现代码，包含了SD协议，usb实现协议(The implementation code of EMMC protocol)
xapp495(1)
- 实现HDMI的receiver和transmitter，来源xilinx xapp(Implement HDMI interface 1.0, including receiver and transmitter,from Xilinx xapp)
FIFO_UVM
- fifo uvm this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output(this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving prop
summer camp xdc
- Design constraints define the requirements that must be met by the compilation flow in order for the design to be functional on the board • Over-constraining and under-constraining is bad, so use reasonable constraints that correspond to your requ
can_ipcore
- 转自opencore 里的代码，希望能有用。(Get from opencore.Hope it can helpful.)