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  1. Fre_Multi_Ctrl_1114

    0下载:
  2. 实现camerallink任意位的串并转换(Implementation of camerallink arbitrary bit series conversions)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-04-29
    • 文件大小:4.43mb
    • 提供者:非要起名字
  1. AXI-full

    0下载:
  2. axi协议中的full子协议,可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)
  3. 所属分类:VHDL/FPGA/Verilog

  1. ds18b20

    0下载:
  2. ds18b20单线温度传感器驱动,可直接上板。包括工程文件。(DS18B20 single line temperature sensor drive, can be directly on the board.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-04-30
    • 文件大小:23kb
    • 提供者:橙子很好吃
  1. i2c_slave

    0下载:
  2. iic slave端,项目中已经用过,可用适用所有传输速率,板间通信,接口少的情况下,可用该程序实现多参数传输,状态监控。(The IIC slave terminal has been used in the project. It can be applied to all kinds of transmission rate, inter board communication and less interfaces. The program can achieve multi param
  3. 所属分类:VHDL/FPGA/Verilog

  1. device_dri

    0下载:
  2. 该程序结合iic驱动程序,可用自动检测硬件的寄存器配置参数是否正确,项目中已使用过(With the IIC driver, the program can automatically detect whether the hardware's register configuration parameters are correct. The program has been used in the project.)
  3. 所属分类:VHDL/FPGA/Verilog

  1. i2c_ctr

    0下载:
  2. 标准iic通信协议,项目中已经使用过,下载可直接上项目(The standard IIC communication protocol has been used in the project. On the basis of IIC, the configuration and detection function of the register can be added.)
  3. 所属分类:VHDL/FPGA/Verilog

  1. pipe25_rc5

    0下载:
  2. pipe可以用于绘制随机petri网和系统性能分析(pipe for help leaner in start stage get more about how to conduct petri net)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-04-29
    • 文件大小:1.97mb
    • 提供者:tiashiaimeili
  1. deadzone

    0下载:
  2. 代码功能是实现脉冲信号的死区控制。根据输入脉冲实现10us的死区,避免IGBT直通。(The code function is to realize the dead zone control of the pulse signal. The dead zone of 10us is realized according to the input pulse, and the direct connection of IGBT is avoided.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-04-29
    • 文件大小:1kb
    • 提供者:FollowSky
  1. Two_Level_SVPWM

    0下载:
  2. 代码为两电平SVPWM调制算法的Verilog程序。包括扇区划分、时间计算、死区控制等。(The code is the Verilog program of the two level SVPWM algorithm. It includes sector division, vecter calculation, dead zone control and so on.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-04-29
    • 文件大小:5.86mb
    • 提供者:FollowSky
  1. buffer

    0下载:
  2. Hi iam Ramana a research scholar,doing my phd from sathyabama university. Title: Designa video codec h.264 processor using verilog hdl. i request you to send video codec H.264 on Verilog hdl. regards D Ramana, M.Tech(Ph.D) SATHYABAMA
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-04-29
    • 文件大小:45kb
    • 提供者:ramanna
  1. led_test

    0下载:
  2. 基于Verilog硬件语言的流水灯设计,可以实现4个led灯按照流水灯的形式闪亮。(ased on the flow lamp design of Verilog hardware language, 4 LED lights can be realized in the form of flowing light.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-04-29
    • 文件大小:1.28mb
    • 提供者:悠悠行人
  1. ECG_ADS

    1下载:
  2. ads8684四路通道采样驱动程序,并且有简单的注释说明,能够根据需要修改模拟信号的采样范围(ads8684 drivers(verilog))
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2018-05-02
    • 文件大小:1.43mb
    • 提供者:blt
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