资源列表
Q3.tar
- hdl using verilog lenguage
Q2.tar
- vereilog design files for beginer
Q1.tar
- implementation of basic elecronics components using verilog HDL
Assignment-2.3.tar
- HDL code using verilog
Assignment-2.2.tar
- verilog-HDL codes for different basic digital circuits elements
Assignment-2.1.tar
- verilog codes for different basic digital circuits elements new
Assignment-1.3.tar
- verilog codes for different basic digital circuits elements
exp_fft_test_724
- 在quartus软件中调用FFT的IP核，编辑IP核的驱动模块，使得IP核读入数据进行处理，输出数据。使用modelsim进行联合仿真。(In the quartus software, the IP kernel of FFT is called, and the driver module of the IP kernel is edited, so that the IP kernel is read into the data for processing and output data
CAR_LI2
- DE1-SOC实验开发板和Verilog HDL语言的交互式程序作品，选择避障小车作为课程设计题目，并根据选题制定了如下设计需求： 1.能实现基本的避障小车功能，即躲避障碍，变速，计分，计时显示游戏开始、进行和结束画面； 2.能实现人机交互功能，玩家可通过外接键盘或DE1-SOC开发板自带按键和开关操作小车转向； 3.能通过VGA在显示屏中显示，并且能达到5Hz的刷新频率； 4.能实现自定义小车和障碍物皮肤的功能；(DE1-SOC experiment development board
fpga-b210-verilog
- usrp系统，B210产品的FPGA源码，还是比较有价值的。(The USRP system, the FPGA source of the B210 product, is still more valuable.)
VHDL简易电子琴设计(1).doc
- 这是一个简单的基于vhdl的电子琴，有自动播放和使用按键来制作不同的音色。(The design of a simple electronic organ based on VHDL, with the automatic playing and the use of keystrokes to make different tones)
spi_master
- 用Verilog写的SPI代码，可读可写，刚仿真完，还没上板，尴尬，主要是官方限制不上传就不能下载～～～～～～～～～～～～～～ 下面的英文是百度翻译过来的，鬼畜的我都不知道啥意思～～～～(The SPI code written in Verilog is readable and writable. After the simulation is finished, it is not yet on board. Awkwardly, it is mainly that official r