资源列表
ReceiveCypress3
- 无线模块PTR6100的verilog数据接收控制代码-code of wireless module of PTR6100 based on verilog
ADS0
- AD7475采样芯片控制器，并转换成16bit并行数据-AD7475 sampling chip controller, and converted into a 16bit parallel data
ma_slice_temp
- verilog code temp h-verilog code temp hahahah
fd32_c.rar
- 32位数据锁存器，用于数据锁存，测试可用，实际使用过,latch，32bits.
hdb3
- 实现了用vhdl语言完成在编码过程中的插B功能，-vhdl hdb3
counter_advanced
- A counter that starts from 0 and increments mod 16 on each rising edge of the clock
EDA
- eda：用VHDL设计一个七段数码管，在led 上显示0——9的数字-eda: VHDL design with a seven-segment digital tube, led display in the 0- 9 numbers
encoder_interface
- 正交编码器接口 用于正交四倍频电路 伺服驱动器常用-Quadrature Encoder Interface circuit for quadrature servo drives commonly used frequency
dac7554_wr
- 本程序为fpga控制dac7554输出，用状态机来写时序，亲测可用-The procedures for the fpga control dac7554 output, the state machine to write timing, pro-test available
ASK_two
- 幅度键控调制是数字调制中 最为基本调制方式之一，这里的 文件是幅度键控调制的FPGA Verilog 文件-Amplitude shift keying modulation is one of the most basic digital modulation modulation, where the file is amplitude shift keying modulation FPGA Verilog file
led_controller_register
- 使用VeirlogHDL实现的一个LED数码管控制器-A LED controller implemented with VerilogHDL program langrage
mul
- 使用Verilog实现的原码4位数的移位乘法器-Using Verilog to realize the original code 4 bit shift multiplier