资源列表
verilab_dvcon2012_uvm_cooper
- Getting Started with UVM by Verilab
SystemVerilog_Synopsys
- systemverilog introduction by synopsys
ActelFPGA
- ACTEL FPGA system is introduced, the older the FPGA
alu
- Code to synthesize Arithmetic Logic Unit
MaxMovie 老干妈
- 演示demo 更清晰更明了 快速便捷 简洁。(The demo demo is clearer and clearer and faster and simpler.)
src
- v6 1x 3.125G rapidio协议工程代码(xilinx v6 rapidio data transmission protocol Practical project application engineering code)
v
- statistical signal processing,verilog
quartus和modelsim中使用mif和hex文件1
- quartus和modelsim中使用mif和hex文件1(fpga modelsim mif hex)
squareLoop
- 利用平方环法提取同步载波的FPGA实现的仿真(FPGA implementation of synchronous carrier extraction using square loop method)
STM32与FPGA通信
- stm32与fpga之间的通信，协议是SPI的，可双向通信（双向通信需要自己例化，只例化了fpga到stm32）(Communication between STM32 and FPGA, the protocol is SPI, two-way communication (two-way communication needs to be taken as an example, only FPGA to STM32))
test_28
- 系统时钟选择时钟模块的1Hz时钟，黄灯闪烁时钟要求为1Hz，红灯15s，黄灯5s，绿灯15s(The system clock selects the clock of the clock module of the 1Hz, the yellow light scintillation clock is required for 1Hz, the red light 15s, the yellow light 5S, the green light 15s)
McBSP_8bit_Asyn
- 基于FPGA的Mcbsp通信源码，经过项目实测检验(Mcbsp communication source code based on FPGA,Through the test of the project.)