资源列表
frehp
- 基于频率抽样方法实现Ⅰ型FIR数字高通滤波器-Based on the frequency sampling method to achieve type Ⅰ FIR digital high-pass filter
clk_divide5
- 五分频电路verilog源码，包含测试文件-Five-frequency circuit verilog source code, including test file
DAC0832_control
- 用verilog HDL编程实现的基于DAC0832的三角波信号，可借鉴编程实现DAC0832芯片控制-Programming with verilog HDL DAC0832-based triangular wave signal, we may learn programming DAC0832 chip control
Cllk20Mto10
- 分频器，将20Hz的时钟信号分频到10Hz-Divider, the clock signal frequency 20Hz to 10Hz
writing
- 关于RAM/ROM的一个写操作的程序，语言为verilog-On RAM/ROM, a write operation procedures, language verilog
GIAIMA38
- Card decode code from 38
adc0809
- ADC0809驱动，VHDL语言描述，开发环境QUARTUS-ADC0809 driver, VHDL language, development environment QUARTUSII
alu
- airthmatic & logic unit
clock_design
- 用VHDL实现了一个电子时钟的功能，能同时显示分/秒-VHDL implementation with an electronic clock function, can display minutes/seconds
adcint
- 基于FPGA，实现控制ADC0809对模拟信号的采样输出-Based on FPGA, to control the ADC0809 to the analog signal sampling output
blink
- State machine that blinks leds. Designed for Altera DE2-115 board.
infrared_receive
- 红外接收处理，根据外部波形记录波形的高低电平时间，从而得到波形数据。-Infrared receiver processing, according to the external waveform waveform record high and low times, resulting waveform data.