资源列表
FPU
- 32位单精度浮点运算单元,遵从IEEE 754标准，持浮点加、减、乘、除等运算。-32-bit single-precision floating-point unit；comply with the IEEE 754 standard；support floating-point add, subtract, multiply operations.
cpld_ads7844_50M(9-24)
- 用ads7844采集数据，用cpld做时序控制，通过串口观察和记录采集结果，用verilog编写，通过开发板验证-Collected data using ads7844 timing control with cpld verilog prepared by the serial observe and record collection results through the development board verification
FPGA_IIC
- 这是我编写的FPGA控制IIC的程序，用来配置型号为24C02的EEPROM，已经通过验证。-This is my own Verilog HDL program for IIC control, it can configure the EEPROM named 24C02, and the program have been tested.
DE2_115_Default
- D2-115学习源码，功能配置，音频功能，LCD控制，视频同步产生器-Learning source D2-115, the functional configuration of the audio function, LCD control, video sync generator
OV7670_Verilog
- 硬件方式初始化OV7670代码，使用Verilog，I2C_Controller.v为底层SCCB 驱动文件； I2C_CCD_Config.v为初始化参数在此文件中配置；cmos_top.v为硬件读取OV7670输出时序； 另外需要给OV7670 输入XCLK时钟， 可以是 50MHZ-Hardware initialized OV7670 code using Verilog I2C_Controller.v the underlying the SCCB driver fil
dw8051-used-in-FPGA
- 自己下载的dw8051核，并在atlys fpga开发板上运行成功。其中rom和ram都已经生成，4个并行I/O口也有。编程语言是verilog。另外，还有hex转in文件的小软件，以及Uedit这个文本编辑器，它是用来给dw8051的rom载入程序的。-The the dw8051 nuclear, download and run atlys fpga development board. Rom and ram have been generated, there are four par
ImageRotate
- 利用verilog实现图像旋转。本程序是基于XILINX公司的ISE实现的。-Verilog image rotation. This procedure is based on XILINX' s ISE.
ImageRotate
- verilog实现图像旋转，可终合，并带有Testbench-verilog image rotation, and can be a final, and with Testbench
VHDL
- 表决器 奇校验器 3位比较器 4选1 数据选择器-The odd parity voting 3 comparator election of a data selector
fft16
- 256点的FFT/IFFT变换VERILOG代码核。-256-point FFT/IFFT transform VERILOG code that nuclear.
sqrt
- VERILOG描述的开平方模块核，开方运算是FPGA或ASIC设计中所需要的核心运算模块。-VERILOG descr iption of open square modules nuclear root operation is the core computing module FPGA or ASIC design.
divider
- verilog 实现的除法运算器，可以进行修改。实现更多位宽的数据。-verilog implementation of division operation can be modified. Achieve more wide data.