资源列表
mimasuo
- 数字密码锁 sjtu 用于教学 basys2板子-digital codelock for SJTU
ise1
- ise教程,Xilinx FPGA/CPLD设计手册 Xilinx公司推荐FPGA/CPLD培训手册-ise for Xilinx FPGA/CPLD
ad_control
- 用verilog实现对AD7656的控制，包括AD的启停、数据的读入。-control the AD7656 to work properly
AD7793
- 运用VHDL语言，实现AD7793芯片的采样程序和SPI的通讯程序，可以将该子模块加载到主程序中。-VHDL language to achieve the AD7793 chip sampling procedures and SPI communication program, this sub-module is loaded into the main program.
xufeng_cdr
- 软件CDR 设计，在LATTICE 平台上验证通过，含说明PPT。Lattice soft cdr-Lattice soft cdr
uart-code-(Verilog)
- uart 源码 Verilog CPLD -uart code Verilog CPLD
clock
- 时钟分配电路，输入为时钟信号CLK，输出为信号F0~F5，这六个信 号中只允许有一个为高电平，F0、F2、F4的持续时间为2个CLK，F1、F3、F5的持续时间为4个CLK。 -A clock distribution circuit, the input clock signal CLK, the output signal F0 ~~ F5, the six signal only allowed to have a high level, F0, F2, F4 duration o
dma_ahb
- 挂靠在AMBA2.0的AHB总线上的DMA装置，用于直接发起数据传输。-Anchored the DMA devices the AHB bus AMBA2.0, for initiating data transfer.
VHDL_Ethernet
- VHDL实现的以太网测试仪器，可以根据配置生成各种模式的以太网数据报文，并对接收到的以太网数据进行统计。-VHDL realization of Ethernet test instrument can generate a variety of modes depending on the configuration of Ethernet data packets, and receives Ethernet data statistics.
Verilog
- RAM ,IFFO实现字节的存储器设计，经过验证-RAM, IFFO bytes of memory design, proven
8255A
- 8255a 做输入输出作用，LED流水灯操作-The Harris 82C55A is a high performance CMOS version o the industry standard 8255A and is manufactured using self-aligned silicon gate CMOS process (Scaled SAJI IV).
UART-SPI-I2C-VGA
- 里面有i2c,uart,spi的代码，也是从别的地方下的觉得还不错,，与大家分享一下，做个参考-I2c, uart, spi code inside, but also from elsewhere feel pretty good, and we share with you, to be a reference