资源列表
clock
- 时钟分配电路，输入为时钟信号CLK，输出为信号F0~F5，这六个信 号中只允许有一个为高电平，F0、F2、F4的持续时间为2个CLK，F1、F3、F5的持续时间为4个CLK。 -A clock distribution circuit, the input clock signal CLK, the output signal F0 ~~ F5, the six signal only allowed to have a high level, F0, F2, F4 duration o
dma_ahb
- 挂靠在AMBA2.0的AHB总线上的DMA装置，用于直接发起数据传输。-Anchored the DMA devices the AHB bus AMBA2.0, for initiating data transfer.
VHDL_Ethernet
- VHDL实现的以太网测试仪器，可以根据配置生成各种模式的以太网数据报文，并对接收到的以太网数据进行统计。-VHDL realization of Ethernet test instrument can generate a variety of modes depending on the configuration of Ethernet data packets, and receives Ethernet data statistics.
Verilog
- RAM ,IFFO实现字节的存储器设计，经过验证-RAM, IFFO bytes of memory design, proven
8255A
- 8255a 做输入输出作用，LED流水灯操作-The Harris 82C55A is a high performance CMOS version o the industry standard 8255A and is manufactured using self-aligned silicon gate CMOS process (Scaled SAJI IV).
UART-SPI-I2C-VGA
- 里面有i2c,uart,spi的代码，也是从别的地方下的觉得还不错,，与大家分享一下，做个参考-I2c, uart, spi code inside, but also from elsewhere feel pretty good, and we share with you, to be a reference
fpga_UDP_NET
- fpga驱动dm9000，通过网口向上位机发送数据。底层为verilog，上层Nios为c。-fpga driver dm9000, send data through the network port up crew. The underlying verilog, upper Nios c.
USB2.0IP
- usb2.0的IP核，对于USB接口通信的FPGA设计有很大帮助，对于接口硬件的控制更为灵活。 有详尽的USB2.0协议说明-usb2.0 IP core for FPGA design of the USB interface communication, more flexible control interface hardware. Detailed USB2.0 protocol descr iption
HiSPi_receiver_v4.0_XP2
- 支持美光HiSpi串行接口转12并行数据输出的FPGA程序-a project that support Hispi protocl
jiarao4
- 加扰与解扰，VHDL实现。初始寄存器值为1产生的m序列。-Scrambling and descrambling, VHDL. Initial register value 1 of the m-sequences generated.
scramble
- 基于VHDL实现加扰器解扰器的设计，与仿真。-VHDL-based scrambler descrambler design and simulation.
VGA_7123
- verilog adv7123 VGA 彩条测试程序-the verilog adv7123 VGA color bar test procedures