资源列表
fpga_UDP_NET
- fpga驱动dm9000，通过网口向上位机发送数据。底层为verilog，上层Nios为c。-fpga driver dm9000, send data through the network port up crew. The underlying verilog, upper Nios c.
USB2.0IP
- usb2.0的IP核，对于USB接口通信的FPGA设计有很大帮助，对于接口硬件的控制更为灵活。 有详尽的USB2.0协议说明-usb2.0 IP core for FPGA design of the USB interface communication, more flexible control interface hardware. Detailed USB2.0 protocol descr iption
HiSPi_receiver_v4.0_XP2
- 支持美光HiSpi串行接口转12并行数据输出的FPGA程序-a project that support Hispi protocl
jiarao4
- 加扰与解扰，VHDL实现。初始寄存器值为1产生的m序列。-Scrambling and descrambling, VHDL. Initial register value 1 of the m-sequences generated.
scramble
- 基于VHDL实现加扰器解扰器的设计，与仿真。-VHDL-based scrambler descrambler design and simulation.
VGA_7123
- verilog adv7123 VGA 彩条测试程序-the verilog adv7123 VGA color bar test procedures
TAXI_TOLL_1_1
- 实现出租车自动计费器 能进行LCD1602液晶显示。硬件平台：Xilinx Spartan3E -Use VHDL languange to achieve the automatic taxi meter and display cost,waiting time and distance on the LCD1602 . Hardware platforms: Xilinx Spartan3E
usb-blaster-driver-for-win-7
- USB BLASTER WIN 7 驱动, 绝对能用,亲测-USB BLASTER WIN 7 drive absolutely can pro-test
Mul32
- Verilog语言编写的单精度浮点数乘法器-The Verilog language of single precision floating point multiplier
CPLD-digital-clock-design
- 基于CPLD实验板的多功能数字钟设计，运用VHDL编写程序-Multifunction digital clock design based on CPLD experimental board, the use of VHDL programming
DMA_TOP
- vhdl code of dma module
rs422
- RS-422的VHDL实现，代码测试能用-RS-422 VHDL implementation code test can be used