资源列表
DIGITAL-SIGNAL-PROCESSING-WITH-FPGA
- 数字信号处理的FPGA实现最新版的源代码,涉及FFT变换、IIR、FIR数字滤波器等的verilog及vhdl代码-<digital signal processing with FPGA> (the latest version) . the source code involving FFT transform, IIR, FIR digital filters by verilog and vhdl.
ZedBoardyuanlitu
- zedboard原理图详细,PCB板焊接方便,每个接口表明清楚。-Zedboard schematic in detail, PCB board welding is convenient, each interface that clearly.
fm
- 用matlab实现了数字正交解调,叙述了数字正交解调算法的过程与原理-Matlab digital quadrature demodulation, describes the process and principle of digital orthogonal demodulation algorithm
UART_Send_handle
- 这是一个很好的基于verilog的串口通信422模块,已经经过多次验证,绝对可靠,可直接使用,本人已在工程中多次使用,无误差-This is a good serial communication based on Verilog 422 module, has been repeatedly verified, absolutely reliable, can be used directly, I have repeatedly used in the project, no error
verilog-ManchesterCoding
- verilog实现的曼彻斯特和差分曼彻斯特编码。压缩包中有源码和结果截图,代码又注释。-The implementation of Manchester Coding and differential Manchester Coding. The file has the source code and the picture of the result. The code is explanatory.
scrambler
- Verilog编写的ADC加扰程序(scrambler)里边附有加扰器的说明,实验可以把数据打散,可自行写testbench测试-Verilog prepared by the ADC scrambled program (scrambler) inside with scrambler descr iption, experimental data can be broken up, write their own testbench test
ad9226_verilog
- AD9226在Sparten6上的FPGA代码实现,测试通过。-AD9226 Sparten6 FPGA code on the test, the adoption.
audio_verilog
- AUDIO音频模块AN831的录音及播放FPGA代码,测试通过-AUDIO audio module AN831 recording and playback of FPGA code, the test passed
ddr3_verilog
- DDR3读写在FPGA上的实现代码,经测试通过-DDR3 read and write FPGA implementation of the code, the test passed
ppscode
- verilog代码,输出秒脉冲,用于采集同步-verilog code, second pulse output for synchronization acquisition
EMIF
- 这是DSP的EMIF总线和FPGA通信的实例,已经测试能用-This is DSP EMIF bus and FPGA communication as an example, has been testing can be used
oledv1.2
- zedboard OLED显示 verilog程序-Zedboard OLED display verilog program