资源列表
USB3.0specification(chinese)
- USB3.0的中文技术规范，包含结构规范和电气规范，适合英文不佳的工程师参考设计。-Chinese USB3.0 specification, including structural and electrical specifications for reference design engineers with poor English.
verilog-Design
- 英文的verilog设计手册，内容详尽，专业-Verilog design manual in English, detailed, professional
CIEDE2000
- CIEDE2000计算实例，每个步骤都有，计算最新的色差公式-Ref: G. Sharma, W. Wu, E.N. Dalal,"THE CIEDE2000 COLOUR-DIFFERENCE FORMULA: Implementation Notes, Supplementary Test Data, and Mathematical Observations," submitted to COLOR RESEARCH AND APPLICATION, Jan 2004.
DAC5662
- DAC5662 verilog control code
SDH1
- SHD 详细设计,包含各种文档，以及VERILOG 源代码-SHD detailed design, including all documents
dac
- DA芯片输出控制 SPI协议 只写不读 FPGA用 verilog-DA-chip SPI protocol output control does not read write-only FPGA with verilog
hdlc_encode
- 基于Verilog的HDLC解码器。输出外接485进行差分输出。-HDLC-based Verilog decoder. Output of an external differential output 485.
txc_ad9957ctrl
- ad9957芯片配置程序，包括将并行18位数据专程spi口传输。基于quartusII创建-ad9957 chip configuration procedures, including a special trip to the parallel 18-bit data transfer spi port. Created based on quartusII
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
cycloneIII_3c120_dev_dsp_example_ChA
- 使用altera FPGA的软件无线电完整项目代码-Altera FPGA software radio using the full project code
fifo-VerilogHDL
- 利用VerilogHDL语言编写的同步FIFO，异步FIFO的编写及其注释-VerilogHDL language using synchronous FIFO, asynchronous FIFO, write and comment
mycpri
- CPRI：采用数字的方式来传输基带信号,其数字接口有两种，标准的CPRI和OBSAI接口。CPRI(The Common Public Radio Interface)定义了基站数据处理控制单元REC(Radio Equipment Control)与基站收发单元RE(Radio Equipment)之间的接口关系，它的数据结构可以直接用于直放站的数据进行远端传输,成为基站的一种拉远系统。-CPRI IP core xilinx examples