资源列表
Phase1111_Tracking
- 使用Verilog编写的相位跟踪器，可以有效解决锁相环中的相位跟踪问题，ISE12.2下编译通过-Written in Verilog phase tracker can effectively resolve the PLL phase tracking, ISE12.2 compiled by
Timing1111_Symcronization
- 使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过-Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by
tdc-gp21-spi
- spi通信，tdc-gp21的spi通信程序-spi communication, tdc-gp21 spi communication program
ingress
- Verilog 实现1588协议的报文解析功能-Verilog 1588 packet analysis function
PipelineSim
- 一个计算机原理课程设计的作业，5级流水线CPU，指令集到代码均为自己设计，有最终报告文档，组建说明，并行除法，16位字长，定长指令，Verilog源代码，顶层设计图。结构简单，冲突解决方式也很简单，代码量小。-A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of par
lms
- 文件中为lms算法的ise工程，其中包含了lms算法的fpga实现的verilog程序以及testbench，很好的在FPGA上实现了lms算法，还有一些调试程序的总结-Ise project file for lms algorithm, which contains the lms algorithm fpga verilog program to achieve and testbench good lms algorithm implemented on FPGA debugger su
dds-5
- 基于FPGA cyclone III EP3C16F484C6的dds正弦波发生器，频率可调-the dds sine wave generator based on the FPGA cyclone III EP3C16F484C6 , frequency adjustable
EtherCAT_IPCore_Altera
- EtherCAT 从站控制器芯片ET1800及其IP_core应用-EtherCAT Slave Controller IP Core for Altera FPGAs
Tutorials
- Mentor graphics FPGA设计软件DK design suite PDK tutorial,该软件是基于high level synthesis，使用handle c设计。-Mentor graphics FPGA design software DK design suite PDKs the tutorial, the software is based on high level synthesis, using the handle c design.
sram_fifo_uart
- 用verilog HDL编写的SRAM+FIFO+UART模块，欢迎各位指点 -Welcome to the guidance written in verilog HDL SRAM+FIFO+UART module
sram
- sram的verilog控制程序，有比较详细的介绍，希望有所帮助。-sram verilog control procedures, a more detailed introduction, hope that helps.
verilog_hitag
- 使用verilog语言实现HITAG2加密算法的实现，即硬件实现 已经验证与C语言结果一致-Use the verilog language HITAG2 encryption algorithm realization that the hardware implementation