资源列表
verilog-encoder
- JPEG的編碼器 使用VERILOG以硬體實現 也使用MODEL模擬驗證-JPEG encoder using the VERILOG hardware implementation is also used to simulate authentication MODEL
BT656_RGB
- BT656转RGB的算法实现代码，使用VORILOG语言编写-BT656-->RGB, verilog
eda
- 南京理工大学EDA实验多功能数字钟+闹钟+dds+am调幅。-Nanjing University of EDA test multifunction digital clock+ alarm+ dds+ am AM.
FPGAapFFT
- 介绍采用FPGA器件实现apFFT算法，精度高于模拟式测量，并且适用性强、成本低-Describes the use of FPGA devices to achieve apFFT algorithms, accuracy is higher than an analog measurement, and applicability, low cost
main
- HDMI 1分4源码 芯片方案：IC EP9134 IC 74HC4052D-HDMI 1 source four-chip solution: IC EP9134 IC 74HC4052D
main
- HDMI1分2程序 芯片方案：IC EP9132 IC 74HC4052D 调试通过-HDMI1 sub-2 program-chip solution: IC EP9132 IC 74HC4052D debugging
decode_64_66
- 自编的64B/66B解码程序，做毕业设计的时候写的。-The decoding process 64B/66B , written when i am in the school。
task2
- Verilog语言，可在QuartusII正确运行，实现远程控制系统，利用异步串行通信，PC发送数据FPGA接收，实现本地回环模式。-清华大学电子课程设计：Verilog language, you can QuartusII correctly, remote control systems, using asynchronous serial communication, PC to send data received FPGA to achieve the local loopback
calculator_final
- 清华大学电子课程设计：Verilog，QuartusII可正确运行，可下载到FPGA上，音乐计算器，完成两个三位数的运算，有注释，很强大-Verilog, QuartusII run correctly, can be downloaded to the FPGA, music, calculator, completed two three-digit operations, there are notes, very powerful! !
i2s_interface
- iis的verilog代码，符合iis协议标准，来自opencores网站。-iis the verilog code, in line with iis protocol standards, from opencores site.
filter
- 用vhdl硬件描述语言写的中值滤波器，主要对尖峰脉冲进行消除。在fpga上实现。-Vhdl hardware descr iption language used to write the median filter, mainly to eliminate spikes. Implemented on the fpga.
8B10B_decode
- 介绍8b/10b的编码与解码的详细流程，主要是基于FPGA的实现方法-8b/10b encoding and decoding described the detailed process