资源列表
LM03806
- LMK03806是一片时钟管理芯片 verilog写的 其中的寄存器设置可能不符合要求 请仔细y阅读文档 已通过仿真-LMK03806 is a clock management chip.This is writed by verilog HDL language,in which the register settings may not meet the requirements.Please read the document carefuly.
OFDM-verilog
- ofdm系统完整源代码，verilog语言编写，在ise平台测试通过-ofdm source code in verilog, run in ise fpga platform
Four-FPGA-design-techniques
- FPGA设计的四种常用思想与技巧，包括乒乓操作、串并转换、流水线操作、数据接口同步化-FPGA design of the four common ideas and techniques, including the operation of ping-pong, SERDES, pipelining, synchronization of data interface
aes_core_128bits
- 高级加密算法verilog版,包括加密和解密算法，其中有s盒，行移位，列混淆等具体算法。-aes encryption for verilog，include subbyte,shiftrow,mixcol,addroundkey.
Foundry-Flash-Verilog-code
- 几大代工厂的flash verilog源代码-flash verilog code
the-8255-LCD
- 设计一串口通信程序，波特率9600，通过RS232串口自环。自动循环发送数据串（设计在程序中）接收并存储和显示该数据串发送数据内容由键盘输入，每串数据不大于8字节。数据串单次发送由按键启动，接收端显示数据串并存储。可查询、清楚已存数据串-The design of a serial communication program, baud rate 9600, through the RS232 serial ring. Automatic cycle to send data string (d
src
- 用Verylog编写的音乐播放器代码,该文件提供了几乎完整的代码-A mp3player s code using Verylog
FM_DemodNew
- FM接收机 基于FPGA的调频收音机的设计 用VEIRLOG语言编程，利用QUARTUSii与MODELSIM联合仿真-FM receiver on FPGA FM receiver design With VEIRLOG language program, use QUARTUSii and MODELSIM joint simulation
arriaIIGX_2agx125_fpga
- Altera公司的Arria II GX系列的原理图和pcb文件，注意，是capture及pdf格式的原理图和allegro格式的PCB文件，稍微修改修改就可以用在您的设计中，让fpga的硬件设计变得简单和高效。- Arria II GX FPGA Development Schematic(caputure and pdf format) and PCB file,very useful for fpga design,let fpga hardware design become easy
VHDL
- 带有CDR和曼彻斯特编解码的串行接口，代码编译仿真成功过-Control Link Serial Interface with Manchester and CDR
Phase1111_Tracking
- 使用Verilog编写的相位跟踪器，可以有效解决锁相环中的相位跟踪问题，ISE12.2下编译通过-Written in Verilog phase tracker can effectively resolve the PLL phase tracking, ISE12.2 compiled by
Timing1111_Symcronization
- 使用Verilog编写的时间同步模块，解决位同步问题，ISE12.2下编译通过-Time synchronization module written in Verilog, bit synchronization issues under ISE12.2 compiled by