资源列表
30S_basketball
- 设计了篮球竞赛30秒计时器。此计时器功能齐全，可以直接清零、启动、暂停和连续以及具有光电报警功能，同时应用了七段数码管来显示时间。此计时器有了启动、暂停和连续功能，可以方便地实现断点计时功能，当计时器递减到零时，会发出光电报警信号。-It designed a 30-second timer basketball competition. This timer functions, can be directly cleared, start, pause, and a row and a ph
NIOSII_TFT_COMS
- 带FIFO的ov7670 FPGA应用程序，经测试可用，望采纳。-With the FIFO the ov7670 FPGA applications used by the test, looking to adopt.
niosii-triple-speed-ethernet
- 这是用sopc搭建的一个工程，实现三速以太网的传输。开发版是3c120-This is an engineering sopc structures, triple-speed Ethernet transmission. The Developer Edition is 3c120
ad7928
- ad7928的采集控制，用verilog HDL语言编写，已在测试板上测试程序。-Ad7928 collection control, use verilog HDL language, and has set up a file in the test board test procedure.
ad9850
- 介绍了用FPGA控制DDS产生任意频率范围之内的可调制正弦波，13位BPSK,ASK等。控制字由串口写入。-verilog control AD9850 to get psk ask
shift-register
- 一个8位的左右移位寄存器电路，输入为时钟信号CLK，方向控制信号D， 输出信号为每个寄存器的状态。 -An 8-bit left and right shift register circuit, the input of the clock signal CLK, the direction control signal D, the output signal of the status of each register.
EMAC6
- verilog实现的FPGA三态以太网链路层通信代码，里面有状态机，并按各个模块的功能分了文件夹，还有说明文档，自定义帧的产生和接收，开发环境为Xilinx ISE，测试无误。-verilog realization FPGA Tri-Mode Ethernet link layer communication code, which the state machine, according to the function of each module sub folder, as well a
verilog串口收发模块程序
- 基于verilogHDL语言的RS232串口收发模块程序
ft245new
- FPGA与ft245之间的通信，可用FTDI公司自带的labview上位机通信软件进行上位机与FPGA之间通信，已测试过，可用-Communication between the FPGA and ft245 available FTDI comes labview host computer communication software for communication between the host computer and FPGA, has been tested, availabl
C6678-FPGA-source-(very-good)
- TI公司8核DSP C6678开发板fpga源码，很好。-TI DSP C6678 fpga code
pci-express-system-architecture.pdf.tar
- PCI Express is a high performance, general purpose Serial I/O Interconnect defined for a wide variety of future computing and communication platforms. The basic premise of PCI Express is that the host PCI software remains compatible with an e
AD_FIFO
- 简单的Verilog程序，针对音频实验板的AD到DA调通试验，下载执行前请按照自己试验环境更改设置-Simple Verilog program for test the AD to DA loop of universal audio test platform. Please configure it according to the test environment before download and implement the program to FPGA