资源列表
消抖模块源代码
- 对fpga中的按键，防摔等部分进行消除抖动(To eliminate the jitter of the key in the FPGA, the fall prevention and other parts)
Desktop
- 状态机简单程序轮流点亮LED小灯采用米勒型状态机(VHDL zhuangtaijishixian)
Desktop4
- VHDL编写的分频器和数码管轮流点亮程序(VHDL shumaguan fenpinqi)
状态机
- 设计一个简单的数字电路用于电子卖报机，要求如下： 报纸价格为1.5元；投币器只接受5角和1元硬币；投币器不找零。当投入金额合适时，报纸出口打开，否则关闭。用Verilog完成设计。(The design of a simple digital circuit for electronic selling machine, the following: The price is 1.5 yuan; the coin only accept 5 cents and $1 coin coin do
equalizer
- matlab code for ZF equalizer
VHDL-和-Verilog-HDL-的区别
- The difference between VHDL and Verilog HDL.
计算器
- 用verilog语言实现了一个计算器alu，实现加减乘除的简单计算。(Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide.)
Desktop
- 实现了3-8译码器的组合逻辑和时序逻辑，正确性已经通过了仿真验证，代码规范(The combined logic and timing logic of the 3-8 decoders are implemented. The correctness has already passed through the simulation verification, the code specification)
spi
- 实现spi写功能，读功能，仿真，板级调试都通过验证了。(achieve write function and read function of spi, simulation is verified)
FIR_filter_stereotype
- 第二类有限冲击响应滤波器60阶常系数verilog(The second type of finite impulse response filter, 60 order,coefficient verilog)
fifo
- IL SAGIT D'UN FIFO EN DEscr iptION DE LANGUAGE vhdl
EthCRC32
- This module calculates ethernet crc32 on fpga using table method