资源列表
E4_4_IIR4Functions
- 用verilog语言实现的一个IIR滤波器，因为现在的ise等工具中没有包含相关的ip核，所以需要手动设计。 -With verilog language to achieve an IIR filter, because now ise and other tools do not contain the relevant ip kernel, so the need for manual design.
file_test
- modeslsim仿真读写文档内容的实现以及显示操作内容的功能-Modeslsim simulation to read and write the contents of the document and display the contents of the operation of the function
simple
- FIRST WORD FALL THROUGH FIFO
n_Bit_Counter
- n bit counter verilog code
clock
- 一个简易的数字钟，可以根据输入的时钟频率来计时-A simple digital clock can be clocked based on the input clock frequency
jsq
- 一个在ise平台上写的计算机小程序，可以计算加减乘除，输入位数为10位，三位小数-A computer on the ise platform to write a small program, you can calculate the addition and subtraction multiplication and division, the input bit is 10, three decimal
seg7
- 数码管实验，包括段选位选，通过了FPGA开发板验证。-Digital tube experiments, including the election of the selected segment, through the FPGA development board validation.
[verilog]dcfifo_256x32
- Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y-This is self-defined Dual-Clock FIFO, using logic lut resources.
axi_master
- DDR3 控制器，axi4_full 模式， burst长度为16，应用于xilinx平台。-DDR3 interface controller， axi4_full working mode with burst length 16, can operate on the xilinx platform.
spi_master
- SPI 控制接口，可支持传输位数的动态配置。-SPI standard controller interface，can support configure dynamically.
crc_unit_16
- 用verilog语言实现CRC16校验，已通过仿真验证。-Use verilog language implementation CRC16 calibration, was validated by simulation
responder
- basys2实现抢答器，Verilog描述语言，实现4人抢答器，功能已验证-Basys2 u5B9 u73B0 u62A2 u7B54 u5668 uFF0CVerilog u63CF u8FF0 u8BED u8A09 uFF0C u5B9E u73B04 u4EBA u62A2 u7B54 u5668 uFF0C u529F u80FD u5DF2 u9A8C u8BC1