资源列表
led_display
- 用硬件描述语言verilog hdl来描述led等的显示。-led display
s2p
- 用硬件描述语言verilog hdl 写的串行转并行代码。-convert serial to parallel
scan_led
- 用硬件描述语言verilog hdl写的实现动态扫描显示的代码。-Using Hardware Descr iption Language Verilog HDL written to achieve dynamic scanning display code.
Butterfly_lovers_beef
- verilog编写的蜂鸣器音乐《梁山伯与祝英台》。系统时钟为50MHz。-Verilog prepared buzzer music Butterfly Lovers . The system clock is 50MHz.
cla_16bit
- verilog 16bit carry lookahead adder-verilog 16bit carry lookahead adder
fec
- RS编码电路 ，包括乘法器的模块和编码部分 RS编码器\mula_0.v RS编码器\mula_1.v RS编码器\rscode.v(The RS encoding circuit includes a multiplier module and an encoding section RS encoder \mula_0.v RS encoder, \mula_1.v, RS encoder, \rscode.v)
qam16 modulator
- QAM16 MODULATOR VERILOG CODE ON FPGA
booth
- 16位booth乘法器的实现：先将被乘数的最低位加设一虚拟位。开始虚拟位变为零并存放于被乘数中，由最低位与虚拟位开始，一次判定两位，会有4种判定结果。(The 16 bit booth multiplier to achieve: first the least significant bit is added with a virtual position. Start a virtual becomes zero and stored in the multiplicand, startin
UART
- uart 的verilog源码，希望对大家有用！(UART Verilog source hope useful for all!)
VHDL代码
- 实现简单的电子拔河比赛，即两按键模拟，计数器计数，比较器进行比较，最后通过LED灯进行直观显示(To achieve a simple tug of war competition, that is, two button analog, counter count, comparator comparison, and finally through the LED lamp for visual display)
pn10
- 用verilog生成11级的pn序列，Xilinx平台(Generating 11 levels of PN sequences with Verilog)
PWM
- VHDL code for PWM Generator with Variable Duty Cycle