资源列表
delay
- 对输入每一路数据进行配置不同时间的延时，在一个存储池内(delay every input channel)
实验1
- 用verilog语言实现译码器,包含数据流文件(Achieve decoder with verilog language, including experimental data stream file)
chapter_listing
- Embedded SoPC Design with Nios II Processor and Verilog Examples
chu_avalon_vga_de2
- Embedded SoPC Design with Nios II Processor and VHDL Examples-VGA
chu_ip_drv
- It contains the C driver (.c and .h) files of IP cores in Parts III and Part IV. Since the driver files are not integrated with HAL, the corresponding files must be manually copied to the software application project directory when a core is used i
de1_build
- The codes in the book are targeted for the DE1 board. Minor modifications are needed for the DE2 board. This directory contains the modified codes. Detailed use is explained in the pdf file within the directory.
de2_build
- De2_build: It contains the FPGA configuration file of the comprehensive Nios II system in Section 16.10.2 and software image files for the DE2 board. These files can be used for quick demo or software development. Note that the files can only be us
clock
- FPGA时钟功能，具备修改时间，闹钟等功能，适合初学者，本人初学时自己写的(just lke the chinese says)
traffic_lab6
- 使用FPGA实现交通上的红绿灯功能，主要是为了学习灵活运用FPGA上的定时功能(just like the chinese say,my english is poor)
VGA_test3
- 利用FPGA实现VGA的驱动，驱动VGA进行工作并通过该功能在显示器上显示一定的内容(my english is poor, so have a look at the chinese)
quartuswork
- vhdl入门实例，一位全加器和一位半加器的quartus9.1程序，可直接运行(VHDL entry examples, a full adder and a half adder quartus9.1 program, can be run directly)
Verilog-HDL基础知识非常好的学习教程
- Verilog-HDL基础知识非常好的学习教程(Verilog-HDL basic knowledge, a very good learning tutorial)