资源列表
Sdram
- 在vivado中调用SDRAM的IP核，并通过数据的读入，读出，验证IP核的使用，文件中有仿真结果时序图。(In the vivado call SDRAM IP core, and read through the data, read, verify the use of IP kernel, the file has simulation results sequence diagram.)
VIVADO 从此开始-2017.1-265_14090262
- VIVADO 从此开始,详细讲解了vivado,FPGA开发工具的使用，对于初学者学习VIVADO工具很有用。(VIVADO from now on, explained in detail the use of vivado, FPGA development tools, for beginners to learn VIVADO tools very useful.)
adder8
- 基于vhdl的八位加法器，以两个四位加法器为基础(Eight bit adder of VHDL)
B_G
- Binary To Gray Conversion
Xilinx ISE14_7破解文件和步骤已测可用
- 对于xinlinx ise的破解文件和步骤说明，亲测可用(here is a package of xilinx ise which could use to break the boundaries)
Comprehensive_FM_IP
- 在vivado平台上的用verilog语言编写的FM直接调制程序(On vivado platform of FM modulation directly program written in verilog language)
Kisi Kisi -20171008
- It is a long established fact that a reader will be distracted by the readable content of a page when looking at its layout. The point of using Lorem Ipsum is that it has a more-or-less normal distribution of letters, as opposed to using 'Content her
20091104164816932
- 资料(document)
pipeline_adder
- 用于快速计算32位加法，共分5级锁存器，4个8位加法器(pipeline_adder it helps you to add 32 bits swiftly if you need more information,may call me by the website account,it's really helpful)
uwghb
- FIG simulation speed, distance, amplitude three-dimensional image, Use of natural gradient algorithm, Suppressed carrier type differential phase modulation.
mux_2to1_4to1_8to1
- design verilog hdl for mux 2to1, mux4to1, mux8to1
Zedboard_Camera_PCB
- camera and zedboard, vga