资源列表
bin2ascii
- Bin to ascii converter, with leading zeros. Room for improvement, remove the leading zeros.
equalizer
- matlab code for ZF equalizer
library ieee
- 四种模式：一共六个灯，1从左到右闪2从右向左闪3从中间向两边4从两边向中间(Four modes: a total of six lights 1 from the left to the right 2 from right to left, 3 from the middle to the two sides to the middle 4from both sides to the middle)
predictive control
- 基于FPGA控制芯片的预测控制和一个完整的控制系统(Predictive control based on FPGA control chip and a complete control system)
microblaze_GPIO
- 基于xilinx 的软核microblaze的GPIO IP核程序(GPIO IPcore program for soft core MicroBlaze based on Xilinx)
IEEE Standard for Verilog 2005
- this book introduces the use of Verilog HDL.
夏宇闻数字逻辑设计
- digital logic design
VHDL语言100例详解
- VHDL language 100 examples
VHDL-和-Verilog-HDL-的区别
- The difference between VHDL and Verilog HDL.
16位超前进位加法器
- 16位超前进位加法器的报告，报告里面含有主代码测试代码仿真结果(16 bit forward adder)
Verilog HDL使用中该注意的问题及一些模块代码
- cpu仿真，提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words in this short file how can I do? just tell you the simulated file and vivado system is 2015)
计算器
- 用verilog语言实现了一个计算器alu，实现加减乘除的简单计算。(Using Verilog language to achieve a simple calculator ALU, computing add, subtract, multiply and divide.)