资源列表
1306151376
- gate example in xilinx
mustafaokanyolcakar
- divide-and-conquer algorithm for finding the position of the largest element in an array
sim
- 调试bcm5396，写入和读取内部寄存器功能。功能验证可以用(Debug bcm5396, write and read the internal register function. Functional validation can be used)
nokia ring tone RTLL
- Nokia ringtones 8051
yii-account-module-master (1)
- mkjhkjh kjhjkhjkhk kjhkjh kjhkj
uart_latest.tar
- UART的VHDL建模代码，是一个标准的IP核(UART's VHDL modeling code is a standard IP core)
HardwareDesignAndModeling
- instruction vhdl persian
xsym
- 数码管显示,试用于初学者的源代码。希望通过(The digital tube displays the source code of the beginner. Hope to pass through)
key_led
- led verilog语言控制 使用quartus的简单实现(led ctrl it's easy)
clock
- 数字时钟，用VHDL语言设计，能调时间，整点响铃(Digital clock, designed in VHDL language, can adjust the time, the whole bell ring)
lab1
- 在vivado上测试通过的fpga流水灯(Test the passing FPGA flow lamp on vivado)
lab3
- 在vivado上测试通过的fpga分频器(FPGA frequency divider tested on vivado)