资源列表
lab4
- 在vivado上测试通过的fpga滤波器(Test the FPGA filter passed on vivado)
基于STEP-FPGA板的简易数字音频播放器
- 基于FPGA的数字音频播放器，将mp3文件通过fpga并外接扬声器进行播放(FPGA based digital audio player, the MP3 file is played through the FPGA and out of the speaker.)
float_adder
- 实现可调维度的浮点数加法运算，内涵各个子模块和testbench(Able to achieve the float numbers adding operation.)
基于FPGA的嵌入式软核设计
- 基于FPGA的嵌入式软核设计，通过搭建软核实现控制(Embedded soft core design based on FPGA and control by building soft core)
AlteraLab1
- To design Fibonacci Sequence using Verilog. SOFTWARES USED: Xilinx Synthesis Tool ISE 9.2i INTRODUCTION. Hardware descr iption language (HDL) is a general-purpose language intended to describe circuits textually,
hamming_fsk
- 基于汉明编码的fsk传输系统，含编码，调制，解调，解码等模块。(FSK transmission system based on Hamming code, including encoding, modulation, demodulation, decoding and other modules.)
i2s
- 用Verilog实现的i2s功能，支持24bit的左右声道 接收和发送。左对齐，延迟1拍。(I2S module, Verilog I2S, up to 24-Bit Data Data Valid on Rising Edge of SCLK)
ram
- 简单的ram程序，实现提取数据，希望对大家有所帮助，提升FPGA编程能力(Simple ram program, the realization of data extraction, hope to help you, improve the ability of FPGA programming)
VHDL verilog教程
- 多种教程包含VHDL以及verilog 收集好久(A variety of tutorials include VHDL and Verilog)
UAET_323_to_flow_led
- VHDL 实现串口收发并点亮流水灯，仿真成功(VHDL realizes serial port transceiver and lighting water lamp)
fir
- fir滤波器源代码及测试程序,有限脉冲滤波器的源程序及测试程序 ,已经通过仿真了(Filter source code and test procedures,Finite pulse filter source and test procedures, has been through the simulation)
FIR_filter_stereotype
- 第二类有限冲击响应滤波器60阶常系数verilog(The second type of finite impulse response filter, 60 order,coefficient verilog)