资源列表
freaq_meter
- It s a code in VHDL for freq_meter
ASSIGNMENT_1
- its an assignment given to us on 2 way traffic controller
GeneradorFunciones
- Sine signal generator with the following I/O entity sinewave is port (clk :in std_logic dataout : out integer range -128 to 127 ) end sinewave -Sine signal generator with the following I/O entity sinewave is port (clk :in std
BCD
- ROM vhdl for binary to BCD
Counter.v
- Custom verilog code for up counter with Interrupt.
alu_32bit_tb
- alu 32 bit using opcode which performs certain operation
HBfir
- 自己编写的半波带滤波器，可应用于抽取滤波器-failed to translate
addN
- A simple ADDN module
waveform
- The waveform of pulse generator code
self-drink-seller-verilog-code
- 饮料自动售卖机的verilog代码，实现各种情况下饮料的购买-self-drink seller verilog code
QD
- 四路抢答器，主持人复位之前抢答算做犯规，复位之后抢答第一个人有效，其余无效。并且均有组别显示与声音示警。-Four Responder, Responder counted reset before the host foul, the first person to answer in an effective after a reset, the rest is invalid. And have a group show with the sound warning.
code_clk_nco
- 码时钟发生器，可灵活配置参数，根据比例得到自己所需的码时钟，可用于扩频通信-CODE CLK MODULE CDMA