资源列表
New_UART_verilog
- 这个是最新的UART的verilog代码，里边含有和UART相关的所有function,比如状态机，接收发送FIFO等相关代码。-New UART verilog sample code,Include FIFO code state mashine code ,recevier/trasmiter code
sdram_ov7670_rgb_vga_640480
- ov7670摄像头工程源码，使用的是黑金开发板，摄像头正常输出640*480的视频图像，对开发人员有很好的参考价值-ov7670 camera project source code, using the black gold development board, camera normal output of 640* 480 video images, the developers have a good reference value
17_usb_device
- 基于NIOS II的USB驱动设计，在FPGA平台上加入NIOS处理器以及需要的ip构成嵌入式系统实现USB数据传输-NIOS II design is based on the USB drive, and the need to join NIOS processor on an FPGA platform ip constitute embedded systems USB Data Transfer
dac9747
- 主要完成ADI公司的DAC（数字-模拟转换器）AD9747的SPI接口及寄存器配置-Mainly to complete ADI' s DAC (digital- analog converter) SPI interface to configure the AD9747 and the register of
sdram_epm570_uart
- 基于CPLD芯片EPM570的verilog hdl串口程序-the UART verilog hdl code based on CPLD chip-- EPM570
BCH_EN
- 基于FPGA的GPS/BD信号发生器中BCH编码发生器模块，使用verilog编写- FPGA-based GPS/BD signal generator BCH code generator module, using verilog write
audio_fft_vga
- 代码使用Verilog HDL实现了使用WM8731对音频进行采样，并且使用ALTERA FPGA实现了频谱计算（FFT），在VGA上显示频谱。-Achieved using the Verilog HDL code using WM8731 audio sampling, and use ALTERA FPGA to achieve the calculated spectrum (FFT), shows the spectrum on VGA.
fpga_fmsc
- 本代码在FPGA上实现了与STM32单片机的FSMC总线通信的时序代码，在ALTERA FPGA上得到验证。-The code on the FPGA to achieve with the STM32 microcontroller timing code FSMC bus communication is verified on ALTERA FPGA.
image-scaling--based-on-the-verilog
- 压缩文件中包含丰富的图像缩放算法，都通过Verilog语言编写的，并包含相应的pdf文件。-Compressed file contains rich image scaling algorithm, written by Verilog language, and contains the corresponding PDF files.
costas_DPSK
- 采用costas环进行DPSK解调的程序。输入数据速率2.4Kbps，载波频率12KHz，采样率1.6MHz， 输入数据位宽12位，快捕带为799.617Hz-Costas ring using DPSK demodulation process. Input data rate 2.4Kbps, carrier frequency 12KHz, sampling rate 1.6MHz, the input data 12 bits wide, fast catching band is 79
gwnseq
- verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）-verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence
i2c-master
- I2C Master Code in Verilog using Finite State Machine.