资源列表
656to601
- 本程序实现视频图象的CCIR656转换CCIR601格式,使用的环境是Quartus II 4.0-the program CCIR656 video image conversion CCIR601 format, The environment is the use of Quartus II 4.0
isatoi2c
- 本程序实现的是ISA转I2C的功能,绝对可用-this program is the ISA I2C transfer function can be absolute
VerilogHDLchinapub
- Verilog HDL硬件描述语言 01简介.PDF 02HDL指南.PDF 03语言要素.PDF 04表达式.PDF 05门电平模型化.PDF 06用户定义原语.PDF 07数据流模型化.PDF 08行为建模.PDF 09结构建模.PDF 10其它论题.PDF 11验证.PDF 12建模实例.PDF 13语法参考.PDF-Verilog HDL Hardware Descr iption Language Introduction 01. P
chip1
- CPLD的程序,分频,微分等,应用于DPLL -CPLD procedures, frequency, differential, etc. can be applied to DPLL
S1_38yima
- 1、本程序模仿3/8译码器的功能 2、由拨码开关输入，led输出。-1, the procedures imitate 3 / 8 decoder function 2, code switching from the allocation of import, export led.
dds-design
- DDS design with vhdl language.
TFT_LCD_IP
- TFT_LCD控制电路CPLD_IP设计-certified CPLD_IP control circuit design
Open_Verilog_International_-_VERILOG-HDL_PLI_Refer
- pli的文档资料，是cadence出的，详细介绍了pli的使用方法-pli document, the cadence is introduced in detail the use pli
diexing
- VHDL编写的蝶形变换，可用于FFT变换-VHDL prepared by the butterfly transform, FFT can be used to transform
fftvhdl
- FFT设计源码：一个FFT设计的VHDL源文件，供参考-FFT design source : an FFT VHDL design source for information
LED47DISP
- 4-7segment led display Verilog code. Implemented at Stratix EP1S25 DSP development board.-4-7segment led display Verilog code. Impl emented at Stratix EP1S25 DSP development boar d.
VHDL_8X8led
- 8X8点阵的VHDL实现，使用10K20，包括顶层原理图-8X8 lattice of VHDL, use 10K20, including top-level schematic diagram