资源列表
counter32
- 基于VHDL的方波产生代码，根据占空比的不同，输出不同方波-Based on square wave generated VHDL code, according to the different duty cycle, the output of different square-wave
qiangdaqi
- 一个关于抢答器的HDL设计，完整源代码 Vhdl编程，编译通过-A Responder on the HDL design, complete source code Vhdl programming, compile
traffic-light
- Verilog based traffic light controller source code
lcd
- 本实验是用LCD1602显示英文 显示“HELLO WORLD!-This experiment is LCD1602 display in English Display "HELLO WORLD!
MotorControl
- This source code is used to control moto controller
parrel_to_serial
- S2p源可以用于实现相关的数据,但不能达到草湖北县外操作-S2p source can be used to implement the relevant data, but cannot achieve grass hubei outside the county operation
FIR_LP
- 简单FIR低通滤波器 ， 阶数6阶，采样频率100KHZ ， 载频10KHz-FIR Filter
1
- preproc code in vhdl
gray
- verilog语言编写的十分频器源码和测试文件-a program of ten divider,with a source and test file,using the verilog language
adconfig
- 一般AD模数转换器的VHDL配置程序，输出为14位串口输出，状态机实现的。-General AD ADC VHDL configuration program, the output is 14 serial output, the state machine implementation.
regfiles
- 寄存器堆 32个寄存器，可实现数据写入和读出，regfiles 时钟控制-Register file 32 registers allow data writing and reading, regfiles clock control
FSM状态机verilog代码
- 能实现状态转换、移位功能的状态机，使用verilog代码编写，能通过modelsim编程实现。