资源列表
barrelshift
- 8-bit parametric barrel shifter
conv_encoder
- TD-LTE中（3.1.7）咬尾卷积码编码器verilog代码-Tail-biting convolutional code encoder verilog code
register
- 用Verilog实现了一个基本寄存器，并且用仿真和led灯来显示了读写数据。-Using Verilog to achieve a basic register, and led lights and simulation to show the read and write data.
slave_spi_ctrl.rar
- SPI 的FPGA控制源代码，用于一般通用的SPI技术，FPGA/CPLD控制的AD数据采集,SPI control course code
HA
- half adder vhdl code
mytime
- Verilog实现的实时时钟 功能，时分秒-Verilog timer
sell
- Verilog 实现自动售货机，现在，自动售货机产业正在走向信息化并进一步实现合理化。例如实行联机方式，通过电话线路将自动售货机内的库存信息及时地传送各营业点的电脑中，从而确保了商品的发送、补充以及商品选定的顺利进行-CLK: standard clock signal, in this case, the frequency for 4Hz Now, the vending machine industry is on her way to the information and fur
89206238_P1
- floating point adder
Adder
- Gate level implementation of two single bit Full Adder & Half Adder.
m
- 本设计实现了一个12级m序列发生器，包含源文件及其测试文件。-This design has realized a level 12 m sequence generator, and the test file contains the source file.
div1hz
- Divisor de a hz con cambio para mas, cambiando los bits
fsm_seq0101
- verilog状态机实现的序列检测器，本人仿真通过，绝对可用，欢迎大家下载学习。-verilog state machine sequence detector simulation by himself, absolutely free, welcome to download the study.