资源列表
quanjiaqi
- 4 级流水方式的8 位全加器-Way flow of 4 full adder 8. . . . . .
divide_by_3
- This module divides the input clock frequency by 3.
multiplier
- Example of doing multiplication showing how to use variable with in process how to use for loop statement algorithm of multiplication
VHDL
- 减法器可以完成VHDL的减法功能，还可以组成8为减法器的功能-Subtraction can be done VHDL subtraction function can also be composed of 8 features for the subtractor
parallel_in_serial_out
- 适用于D/Atlc5620的并行-串行数据转换模块【VHDL】-parallel_in_serial_out driver for D/Atlc5620【VHDL】
dl.sh
- linux cmd line download scr ipt
cyclecoder_decoder
- (7,4)循环码的verilog编码程序，（7，4）循环码的verilog译码程序-(7,4) cyclic code Verilog coding procedures, (7,4) cyclic code the verilog decoding procedure
single_port_ram
- Single port RAM with single read/write addre-Single port RAM with single read/write address
alpha_func
- This alphabet generating program in vhdl with various colors and models, i remodelled the oscillator to do this. maybe it will just for fun.-This is alphabet generating program in vhdl with various colors and models, i remodelled the oscillator to do
priorityencodtest
- parity encoder test bench
SRAM_16Bit_512K_0
- SRAM的ip核，niosii，avalon总线的-SRAM' s ip nuclear, niosii, avalon bus
dds1
- 数字合成函数发生器 初学者最好的教程DDS-dds