资源列表
ADC_TCL5510
- 用verilog编写的源代码 可以对此芯片进行相关操作-Written in verilog source code can be related to the operation of this chip
acc
- This code has function to accumulate
jishuqi
- 电子设计自动化中的计数器的实现程序，基于VHDL语言完成的-Electronic design automation in the realization of counter procedures, based on the VHDL language completed
liuy
- 一个精确时钟的v-log程序，只用一个全局时钟，增加了精确度-An accurate clock in the v-log program, only one global clock, increased accuracy
rightshift
- right shift register VHDL
booth_multiplication
- this verilog code-this is verilog code
shixucaiyangkongzhimokuai
- 时序控制采样模块，可以根据自己的需要对程序进行相应的修改，以采集到自己想要的数据。-Sequential control sampling module, can need according to oneself the procedure with the corresponding revision, they want to collect the data.
NCO
- 指输出频率与输入控制电压有对应关系的振荡电路(VCO)，频率是输入信号电压的函数的振荡器VCO，振荡器的工作状态或振荡回路的元件参数受输入控制电压的控制，就可构成一个压控振荡器。-Refers to the output frequency and input voltage control oscillation (VCO) circuits, corresponding relationship with frequency is a function of the input signal
cronometro1.c
- cronometro atmel 328p code vision avr
ep_rom
- 采用VerilogHdl语言编写的，介于FPGA的EPROM的开发读写-VerilogHdl the use of languages, ranging from the development of FPGA to read and write the EPROM
VHDL03
- 全加器仿真程序代码，本人亲自测试，代码简单，安全无毒。放心下载和使用。-Full adder simulation code, I personally tested the code simple, safe non-toxic. Ease to download and use.
electronic-lock-and-VHDL-design
- 基于Max+Plus II和VHDL的电子密码锁设计-Based on Max+ Plus II electronic lock and VHDL design