资源列表
Debunce
- VHDL 弹跳消除电路，对于FPGA按键很需要-VHDL bounce elimination circuit, it is necessary for the FPGA button
fsk
- 过零检测法设计了一种FSK数字解调器，实现了对FSK数字调制信号的解调，达到了解调的目的-Zero-crossing detection method designed a digital FSK demodulator is realized on the demodulation of FSK digital modulation signals, to understand the purpose of transfer
FiltroRebote
- source code for monoestable in vhdl
LightExp
- 交通灯，基于TPC，5s，3s，其中3s内黄灯可1s闪烁一次。重复。-LightExp code
LED_6
- 基于AT89C51的跑马灯实验，十分简单，适合初学者。-Based on AT89C51 Marquee experiment is very simple for beginners.
vhdl.tar
- 38译码器的VHDL实现，支持linux平台，包含完整的Makefile支持。-38 decoder VHDL, support linux platform, including full Makefile support.
xulie
- 这是一个用VHDL编写的用以通过串到并的转化发送序列，程序调试完全正确，请放心使用-This is a VHDL prepared for use through the string and the conversion to send the sequence program debugging completely correct, please rest assured that the use of
transmitter
- 串口模块程序，可以实现串行发送和接收功能，比特率可以不断调整，数据的长度是可以改变的-Serial port module program, you can achieve the serial send and receive functions, and bit rate can be continuously adjusted, the data length can be changed
t51
- 用VHDL设计一个四舍五入判别电路，其输入为8421BCD码，要求当输入大于或等于５且小于10时，判别电路输出为１，小于5为０，大于等于10时输出为高阻态。 -VHDL design with a rounded judge circuit, its input 8421BCD code require that when the input is greater than or equal to 5 and less than 10, the discrimination circuit ou
softdrink
- 自动售货机verilog源码,含找零功能，通过Modlesim,leonardo仿真，综合-Vending machine verilog source
mul32
- 32位无符号乘法器 采用VHDL语言编写，很容易改为有符号32位乘法器-32-bit unsigned multiplier using VHDL language, it is easy to signed 32-bit multiplier
CANCS
- 用的是able语言 编写的一段程序 可以参考学习使用-Is able to use a program written in a language can refer to learn to use