资源列表
counter
- 基于Xilinix公司的BASYS2板子完成的一个计数器电路以及仿真代码。-Based on a counter circuit board Xilinix company BASYS2 completed and simulation code.
asynchronous-counter
- 4个触发器构成的异步计数器,采用VHDL语言描述-asynchronous counter
s
- 自动售饮料机-Beverage vending machine. . . . . . . . . . . . . . . . . . .
fir_srg
- 该程序是利用Verlag HDL硬件描述语言实现的fir数字滤波器,希望对刚学习verilog的朋友有所帮助。-The procedure is to use Verlag HDL hardware descr iption language implementation of fir digital filters, just want to help a friend learn verilog.
infrared_rx_seg7x8
- 基于FPGA板得程序操作 在数码管上显示并接受红外传输值 -Operating procedures based on FPGA board was displayed on the digital value and accept the infrared transmission
Full-Adder
- Full Adder to add 4 bits of input
div_32bits
- 以ISE为平台,VHDL语言编写的32位补码整数除法器模块,只需在Top模块中调用即可-As a platform to ISE, VHDL language complement 32-bit integer division module, simply call the module to Top
dds_vhdl
- DDS的VHDL程序,相当好,值得下载,共享才是王道-DDS, VHDL program is quite good, worth downloading, sharing is king
VHDL-2FSK
- 基于VHDL的FSK调制与解调, 基于VHDL的FSK调制与解调,-VHDL-based FSK modulation and demodulation
inverter422
- 延时小,功耗小的反相器链设计。HSPICE 仿真网单,。25um工艺-less delay ,low power consumption.
Thyristor_gate_control_pulse_generator
- 一个例子 VHDL代码设计时,它是控制一个例子 晶闸管。-An example VHDL code designs are presented,it is for controlling an example thyristor.
comparator
- it contain source code for comparator module.